Patents by Inventor Chih-Ming Chen

Chih-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369526
    Abstract: A stacked (or vertically arranged) photodetector having at least one contact region on a germanium sensing region. Including the at least one contact on the germanium sensing region reduces the amount of surface area of the germanium sensing region that is interfaced with a substrate (e.g., a silicon substrate) in which the germanium sensing region is included. This reduces the amount of lattice mismatch reduces the amount of misfit defects for the germanium sensing region, which reduces the dark current for the photodetector. The reduced amount of dark current may increase the photosensitivity of the photodetector, may increase low-light performance of the photodetector, and/or may decrease noise and other defects in images and/or light captured by the photodetector, among other examples.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Inventors: Chen-Hao CHIANG, Chih-Ming CHEN, Jing-Hwang YANG
  • Publication number: 20230369521
    Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.
    Type: Application
    Filed: July 12, 2023
    Publication date: November 16, 2023
    Inventors: Chih-Ming Chen, Lee-Chuan Tseng, Ming Chyi Liu, Po-Chun Liu
  • Patent number: 11814731
    Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first processing zone having a first ambient environment and a second processing zone having a second ambient environment disposed at different location inside a processing chamber. A first exhaust port and a second exhaust port are disposed in the first and second processing zones, respectively. A first exhaust pipe couples the first exhaust port to a first individual exhaust output. A second exhaust pipe couples the second exhaust port to a second individual exhaust output, where the second exhaust pipe is separate from the first exhaust pipe. A first adjustable fluid control element controls the first ambient environment. A second adjustable fluid control element controls the second ambient environment, where the first adjustable fluid control element and the second adjustable fluid control element are independently adjustable.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Sheng-Hsun Lu
  • Patent number: 11818864
    Abstract: A tiered immersion cooling system includes a chassis, a cabinet frame slidably mounted to the chassis, an upper immersion tank, and a lower immersion tank. The cabinet frame is slidable between a first internal position and a first external position. Sliding motion of the cabinet frame is in a horizontal direction along a depth of the chassis. The upper immersion tank is slidably mounted to the chassis. The upper immersion tank is slidable with the cabinet frame in the horizontal direction. The upper immersion tank slides relative to the cabinet frame, in a vertical direction along a height of the chassis. The lower immersion tank is positioned below the upper immersion tank in the vertical direction. The lower immersion tank is mounted to slide independently from the cabinet frame, in the horizontal direction. The lower immersion tank slides between a second internal and a second external position.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: November 14, 2023
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Ta-Chih Chen, Chih-Ming Chen
  • Publication number: 20230357002
    Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 9, 2023
    Inventors: Chih-Ming Chen, Yuan-Chih Hsieh, Chung-Yi Yu
  • Publication number: 20230351942
    Abstract: A control device for driving a display device includes a first channel having a first output device. The first output device outputs first transfer data to the first channel according to an enable signal. The first transfer data includes a preamble code and a function code. The first output device includes a preamble-code generator and a function-code generator. The preamble-code generator outputs a bit number of a predetermined value as the preamble code according to the bit number of preamble code. The bit number and the predetermined value are defined by the user. The function-code generator converts each of a function-code number of command codes into a respective bit code, and the function-code number of bit codes are output as the function code according to a lookup table. The mapping relationship between the command code and the bit code is stored in the lookup table.
    Type: Application
    Filed: April 28, 2023
    Publication date: November 2, 2023
    Inventor: Chih-Ming CHEN
  • Patent number: 11804581
    Abstract: A wavelength conversion wheel includes a turnable disc, a wavelength conversion layer, a pressure ring, an anodized layer and a balance weight. The turnable disc has an inner ring portion and a ring-shaped irradiation portion. The ring-shaped irradiation portion is connected to an outer edge of the inner ring portion. The ring-shaped irradiation portion includes a wavelength conversion region. The wavelength conversion layer is disposed on the wavelength conversion region. The pressure ring presses against the inner ring portion and has a first surface facing away the turnable disc. The anodized layer is disposed on the first surface. The balance weight is disposed on the anodized layer, wherein the surface roughness of the anodized layer is 1 ?m to 10 ?m. The wavelength conversion wheel of the invention has better reliability. A projection device with the wavelength conversion wheel is further provided.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: October 31, 2023
    Assignee: Coretronic Corporation
    Inventor: Chih-Ming Chen
  • Publication number: 20230344730
    Abstract: An optimization method includes generating a constrained causal graph according to an observation data received from a distributed unit, performing a finite domain representation planning using the constrained causal graph to generate an action data about a plurality of radio unit parameters after optimization, and outputting the action data to the distributed unit. A number of a plurality of causal variables of the constrained causal graph and a causal structure of the constrained causal graph are determined at a time.
    Type: Application
    Filed: July 20, 2022
    Publication date: October 26, 2023
    Applicant: Wistron Corporation
    Inventor: Chih-Ming Chen
  • Publication number: 20230335906
    Abstract: A wireless transmission system includes a signal-transmitting device and a signal-receiving device. The signal-transmitting device is disposed in a remote-control apparatus for transmitting wireless signals wherein the remote-control apparatus is a mouse. The signal-receiving device is installed on an electronic apparatus to receive the wireless signals and trigger operations in response the wireless signals. The signal-receiving device includes a patch antenna including a dielectric substrate having a first surface and a second surface opposite to the first surface, a ground layer disposed on the first surface, and a radiating metal layer. The radiating metal layer is disposed on the second surface and includes a radiation receiving surface. A first position of the radiation receiving surface is separated from the ground layer by a first distance, and a second position of the radiation receiving surface is separated from the ground layer by a second distance less than the first distance.
    Type: Application
    Filed: February 16, 2023
    Publication date: October 19, 2023
    Applicant: BENQ CORPORATION
    Inventors: Chun-Yi CHANG, Chih-Ming CHEN
  • Patent number: 11789894
    Abstract: An acceleration system includes a plurality of modules. Each of the plurality of modules includes at least one central processing unit, at least one graphics processing unit, at least one field programmable gate array, or at least one application specific integrated circuit. At least one of the plurality of modules includes at least another of the plurality of modules such that the acceleration system is structural and nested.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: October 17, 2023
    Assignee: Wistron Corporation
    Inventor: Chih-Ming Chen
  • Patent number: 11786485
    Abstract: The present invention provides methods and compositions for treating advanced stage non-small cell lung cancer by cyclohexenone compounds.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: October 17, 2023
    Assignee: Golden Biotechnology Corporation
    Inventors: Sheng-Yung Liu, Chih-Ming Chen, Pei-Ni Chen, Hao-Yu Cheng
  • Publication number: 20230319674
    Abstract: An uplink route decision method for a mobile communication system, wherein the mobile communication system determines an uplink path of a user equipment (UE) in the mobile communication system, includes obtaining an attribute of a user plane function (UPF) required by the UE, and determining whether the UPF is located in a local or a remote place according to an artificial intelligence model.
    Type: Application
    Filed: September 8, 2022
    Publication date: October 5, 2023
    Applicant: Wistron Corporation
    Inventor: Chih-Ming Chen
  • Publication number: 20230282476
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device, including a substrate including a first semiconductor material and a semiconductor layer extending into an upper surface of the substrate and including a second semiconductor material with a different band gap than the first semiconductor material. The semiconductor device also includes a passive cap including a first dielectric material and disposed along the upper surface of the substrate and on opposite sides of the semiconductor layer, and a photodetector in the semiconductor layer. The first dielectric material includes silicon nitride.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 7, 2023
    Inventors: Lung Yuan Pan, Chen-Hao Chiang, Chih-Ming Chen
  • Patent number: 11749763
    Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Lee-Chuan Tseng, Ming Chyi Liu, Po-Chun Liu
  • Publication number: 20230266661
    Abstract: A circuit layout patterning method includes: receiving a photomask substrate including a shielding layer; defining a chip region and a peripheral region adjacent to the chip region; forming a design pattern in the chip region; forming a reference pattern by emitting one first radiation shot and a beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein a pixel size of the first radiation shot is greater than a pixel size of the second radiation shot; comparing a width of the reference pattern and a width of the beta pattern; transferring the design pattern to the shielding layer if a difference between the width of the reference patterned and the width of the beta pattern is within a tolerance; and transferring the design pattern of the photomask to a semiconductor substrate.
    Type: Application
    Filed: April 9, 2023
    Publication date: August 24, 2023
    Inventors: CHENG-MING LIN, HAO-MING CHANG, CHIH-MING CHEN, CHUNG-YANG HUANG
  • Patent number: 11735635
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Publication number: 20230253706
    Abstract: An antenna structure includes a feeding radiation element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a switch circuit. The feeding radiation element has a feeding point. The second radiation element is coupled through the first radiation element to the feeding radiation element. The third radiation element is coupled to the second radiation element. The fourth radiation element is coupled to the second radiation element. The fourth radiation element and the third radiation element extend in different directions. The fifth radiation element has a tuning point, and is coupled to the feeding radiation element. The feeding radiation element is disposed between the first radiation element and the fifth radiation element. The switch circuit selectively couples the tuning point to a ground voltage.
    Type: Application
    Filed: March 21, 2022
    Publication date: August 10, 2023
    Inventors: Cheng-Chieh YANG, Chih-Ming CHEN, Po-Yu CHEN
  • Patent number: 11713241
    Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Ming Chen, Yuan-Chih Hsieh, Chung-Yi Yu
  • Publication number: 20230237008
    Abstract: An acceleration system includes a plurality of modules. Each of the plurality of modules includes at least one central processing unit, at least one graphics processing unit, at least one field programmable gate array, or at least one application specific integrated circuit. At least one of the plurality of modules includes at least another of the plurality of modules such that the acceleration system is structural and nested.
    Type: Application
    Filed: April 14, 2022
    Publication date: July 27, 2023
    Applicant: Wistron Corporation
    Inventor: Chih-Ming Chen
  • Patent number: 11662660
    Abstract: A method for manufacturing a semiconductor includes: receiving a photomask substrate including a shielding layer; defining a chip region and a peripheral region adjacent to the chip region; forming a design pattern in the chip region; forming a reference pattern by emitting one first radiation shot and a beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein a pixel size of the first radiation shot is greater than a pixel size of the second radiation shot; comparing a reference roughness of a boundary of the reference pattern and a beta roughness of a boundary of the beta pattern; transferring the design pattern to the shielding layer if a difference between the reference roughness and the beta roughness is within a tolerance; and transferring the design pattern of the photomask to a semiconductor substrate.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ming Lin, Hao-Ming Chang, Chih-Ming Chen, Chung-Yang Huang