Patents by Inventor Chih (Rex) Hsueh

Chih (Rex) Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12376363
    Abstract: A semiconductor device includes a substrate having an I/O region and a core region; a first transistor in the I/O region; and a second transistor in the core region, wherein the first transistor includes a first gate structure having: an interfacial layer; a first high-k region over the interfacial layer; and a conductive layer over the first high-k region, wherein the second transistor includes a second gate structure having: the interfacial layer; a second high-k region over the interfacial layer; and the conductive layer over the second high-k region, and where in the first high-k region is thicker than the second high-k region.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, I-Sheng Chen, Shao-Ming Yu, Tzu-Chiang Chen, Chih Chieh Yeh
  • Patent number: 12369959
    Abstract: A screw with an improved screw head is provided. The screw may include a shank in between a head and a tip. The head may include a plurality of protrusions provided radially along the head. Each of the plurality of protrusions may include a protrusion wall, a leading wall, a trailing wall, and a bottom wall; the trailing wall may include one single trailing surface, the leading wall may include a plurality of leading surfaces, and the bottom wall may include at least one bottom surface.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: July 29, 2025
    Assignee: PRIMESOURCE BUILDING PRODUCTS, INC.
    Inventors: E Erik Timothy, Chih-Hsien Shen, Tse-Kuang Jou
  • Patent number: 12374585
    Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure, and the semiconductor structure. The method includes: providing a substrate having a connection hole thereon, annular protrusions and annular grooves alternately arranged along a direction parallel to a center line of the connection hole being provided on a hole wall of the connection hole; filling a barrier block in each of the annular grooves; removing the annular protrusions along a direction perpendicular to the hole wall of the connection hole; removing the barrier blocks; and forming a connection layer in the connection hole. After the annular protrusions are removed, roughness of the hole wall of the connection hole is reduced, such that a conductive seed layer is prevented from being broken, thereby avoiding generation of voids in the connection layer, and improving performance of the semiconductor structure.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: July 29, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Wei Chang
  • Patent number: 12376323
    Abstract: The invention provides a semiconductor structure, which comprises a GaN gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer on the gallium nitride layer, a polarization boost layer on and in direct contact with the aluminum gallium nitride layer, and a gate liner layer on the polarization boost layer.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: July 29, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Chang, Da-Jun Lin, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Ting-An Chien, Bin-Siang Tsai
  • Patent number: 12374134
    Abstract: An automatic objects labeling method includes: capturing M consecutive image frames at one station of an assembly line. Performing an object detection step which includes selecting a detection image frame that displays an operation using a work piece against a target object from the M consecutive image frames; and calibrating the position range of the target object in the detection image frame; retracing from the detection image frame to select an Nth retraced image frame from the M consecutive image frames; obtaining a labeled image of the target object from the Nth retraced image frame according to the position range; comparing the labeled image with images of the M consecutive image frames to find at least one other labeled image similar to the target object; and storing both the labeled image and the at least one other labeled image as the same labeled data set.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: July 29, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Neng Liu, Hung-Chun Chou, Tsann-Tay Tang
  • Patent number: 12374530
    Abstract: A Faraday shield, a semiconductor processing apparatus, and an etching apparatus are provided. The Faraday shield includes a plurality of conductive slices and a spacer interposed between adjacent two of the conductive slices to electrically isolate the adjacent two of conductive slices from one another. The conductive slices are separately arranged aside one another and oriented along a circumference of the Faraday shield. A coil is wound around the circumference of the Faraday shield.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsiang Chen, Ching-Horng Chen, Yen-Ji Chen, Cheng-Yi Huang, Chih-Shen Yang
  • Patent number: 12374548
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. The photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. In an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.
    Type: Grant
    Filed: April 29, 2024
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Yu Chen, Chih-Cheng Liu, Yi-Chen Kuo, Jr-Hung Li, Tze-Liang Lee, Ming-Hui Weng, Yahru Cheng
  • Patent number: 12374568
    Abstract: A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: July 29, 2025
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shiyu Yue, Sahil Jaykumar Patel, Yu Lei, Wei Lei, Chih-Hsun Hsu, Yi Xu, Abulaiti Hairisha, Cong Trinh, Yixiong Yang, Ju Hyun Oh, Aixi Zhang, Xingyao Gao, Rongjun Wang
  • Patent number: 12376356
    Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.
    Type: Grant
    Filed: February 28, 2024
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Chih-Hao Wang
  • Patent number: 12376417
    Abstract: An image sensor device includes nanostructures for improving light absorption efficiency. The image sensor device includes a substrate, a light absorption region, and a nanostructure array. The light absorption region is over the substrate. The nanostructure array us over the light absorption region. The nanostructure array includes a plurality of nanostructures repeatedly arranged from a top view.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Patent number: 12376148
    Abstract: A station (STA) associated with an access point (AP) receives, from the AP, an indication of an enhanced distributed channel access (EDCA) parameter set. The STA then updates one or more parameters of the EDCA parameter set with respect to a triggered transmission opportunity (TXOP) sharing (TXS) operation.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: July 29, 2025
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Kai Ying Lu, James Chih-Shi Yee, Yongho Seok
  • Patent number: 12372686
    Abstract: A meta optical device is provided. The meta optical device includes an array of meta structures. Each of the meta structures includes a plurality of stacked layers at least including a first layer with a first refractive index and a second layer with a second refractive index. The first refractive index and the second refractive index are different.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: July 29, 2025
    Assignee: TECHNOLOGIES COMPANY LIMITED
    Inventors: Kai-Hao Chang, Shin-Hong Kuo, An-Li Kuo, Chun-Yuan Wang, Yu-Chi Chang, Chih-Ming Wang
  • Patent number: 12374629
    Abstract: An electromagnetic interference (EMI) shielding package structure, a manufacturing method thereof, and an electronic assembly are provided. The EMI shielding package structure includes a carrier, at least one chip mounted on a first board surface of the carrier, an encapsulant formed on the carrier and packaging the at least one chip, an EMI shielding layer formed on an outer surface of the encapsulant, and an insulating layer. The insulating layer includes a spraying portion and a capillary permeating portion. The spraying portion is formed at least part of an outer surface of the EMI shielding layer. The capillary permeating portion is formed by extending from a bottom end of the spraying portion toward a second board surface of the carrier through capillarity, and the capillary permeating portion covers a bottom edge of the EMI shielding layer.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: July 29, 2025
    Assignee: AZUREWAVE TECHNOLOGIES, INC.
    Inventors: Chih-Hao Liao, Shu-Han Wu, Hsin-Yeh Huang
  • Patent number: 12374655
    Abstract: A method includes attaching a wafer to a wafer chuck having a curved surface. The method further includes placing a device die on the wafer, such that a first dielectric layer of the device die is in contact with a second dielectric layer of the wafer, and performing an annealing process to bond the first dielectric layer to the second dielectric layer. The method further includes encapsulating the device die with an encapsulating material, forming redistribution lines overlapping the encapsulating material and the device die, and sawing the encapsulating material to form a plurality of packages.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chih Chiou, Yung-Chi Lin, Yen-Ming Chen
  • Patent number: 12374674
    Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: July 29, 2025
    Assignee: SERIPHY TECHNOLOGY CORPORATION
    Inventors: Tzu-Wei Chiu, Chun-Wei Chang, Shang-Pin Chen, Wei-Chih Chen, Che-Yen Huang
  • Patent number: 12376294
    Abstract: An ESD circuit includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a first ESD current path, a second ESD current path, a biasing circuit and a control circuit. The control circuit is connected between the pad and a first node. The first P-type transistor is connected with the pad, the control circuit and a second node. The first ESD current path is connected between the second node and the first node. The second ESD current path is connected between the second node and the first node. The second P-type transistor is connected with the pad, the control circuit and a third node. The biasing circuit is connected between the third node and the first node. The third P-type transistor is connected with the pad, the third node, and a fourth node. The internal circuit is connected between the fourth node and the first node.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: July 29, 2025
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yun-Jen Ting, Chih-Wei Lai, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
  • Patent number: 12376317
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element partially covering the magnetic element. The semiconductor device structure further includes a conductive feature over the isolation element.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Cheng Chen, Wei-Li Huang, Chien-Chih Kuo, Hon-Lin Huang, Chin-Yu Ku, Chen-Shien Chen
  • Publication number: 20250238086
    Abstract: A waterproof keyboard includes a base plate, a key frame, plural keycaps, a first adhesive layer, plural second adhesive layers and a keyboard film. The key frame is installed on the base plate. The first adhesive layer is installed on a frame top surface. The plural second adhesive layers are disposed on the corresponding keycap top surfaces, respectively. The keyboard film is attached on the first adhesive layer and the plural second adhesive layers. After the keyboard film is subjected to a thermal pressing process, the keyboard film generates at least one concave structure on the frame top surface and plural convex structures on the corresponding keycap top surfaces. The at least one concave structure is attached on the frame top surface through the first adhesive layer. The plural convex structures are respectively attached on the corresponding keycap top surfaces through the corresponding second adhesive layers.
    Type: Application
    Filed: March 4, 2024
    Publication date: July 24, 2025
    Inventors: Zheng-Hong Lai, Chih-Ho Hsu
  • Publication number: 20250239487
    Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.
    Type: Application
    Filed: April 7, 2025
    Publication date: July 24, 2025
    Inventors: Chien-Han Chen, Chien-Chih Chiu, Ming-Chung Liang
  • Publication number: 20250239490
    Abstract: A method includes forming a wafer, and etching a first dielectric layer of the wafer to form a first trench between two dies of the wafer. A first portion of a second dielectric layer of the wafer is directly underlying the first trench. A laser grooving process is then performed to remove the first portion of the second dielectric layer of the wafer and to form a second trench, which is underlying and joined to the first trench. The second dielectric layer includes a corner region where the first trench is joined to the second trench. Portions of a top surface of the corner region closer to a center middle line of the second trench are increasing lower than respective portions of the top surface of the corner region farther away from the center middle line.
    Type: Application
    Filed: May 7, 2024
    Publication date: July 24, 2025
    Inventors: Min-Hsuan Hsu, Ting Hao Kuo, Chih-Sheng Li, Yu-Chia Lai, Chen-Shien Chen