Abstract: A composite connector incudes a connector, a carrier circuit board, and a plurality of filtering units. The connector is disposed on at least one surface of the carrier circuit board, and multiple connection pins are disposed on at least one surface of the carrier circuit board. The carrier circuit board is disposed on a main circuit board or a main circuit board connector of the main circuit board. The filtering units are disposed on the carrier circuit board and connected to part or all of the connection pins to filter out noise on the connection pins. The composite connector of the invention can have a filtering function, thereby reducing the manufacturing cost of electronic devices and increasing the routing flexibility of the main circuit board.

Abstract: Provided is an electronic package, in which a heat dissipating body is formed on an electronic device and is combined with a heat sink so that the electronic device, the heat dissipating body and the heat sink form a receiving space, and a heat dissipating material is formed in the receiving space and in contact with the heat sink and the electronic device, where a fluid regulating space is formed between the heat dissipating material and the heat dissipating body and is used as a volume regulating space for the heat dissipating material during thermal expansion and contraction.

Abstract: A semiconductor device includes a first interconnect structure, a device layer, a second interconnect structure, a diamond layer, a passivation layer, and an electrical connector. The device layer is disposed over the first interconnect structure. The second interconnect structure is disposed over the device layer and comprises a topmost metallization pattern. The diamond layer is disposed over the second interconnect structure and at least revealing a part of the topmost metallization pattern. The passivation layer covers the diamond layer and reveals the part of the topmost metallization pattern. The electrical connector is disposed over the passivation layer and bonded to the part of the topmost metallization pattern.

Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.

Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer and a first alignment layer. The first alignment layer is disposed between the first electrode layer and the ferroelectric layer, and the ferroelectric layer and the first alignment layer have the same crystal lattice orientation. In some embodiments, a material of the first alignment layer has a band gap smaller than 50 meV.

Abstract: A projection device includes a light source device including a light source configured to emit an excitation beam, and a light splitting element, a quarter-wave plate, a filter element, and a wavelength conversion element located on a transmission path of the excitation beam. The filter element includes first and second filter regions and a reflective region, and enables the first and second filter regions and the reflective region to enter the transmission path of the excitation beam sequentially. The excitation beam penetrates through the first and second filter regions, and is reflected by the reflective region to form a reflected beam. The excitation beam passes through the filter element and is incident on the wavelength conversion element, causing the wavelength conversion element to generate a wavelength-converted beam, and the wavelength-converted beam is incident on the filter element.

Abstract: The present disclosure discloses an inspection device and an inspection method. The inspection device includes a first light source, a second light source, a light source controller and a sensor. The light source controller is configured to enable the first light source to irradiate an object under inspection in a first period of an inspection phase, and to enable the second light source to irradiate the object under inspection in a second period of the inspection phase. The sensor continuously senses the reflected light of the object under inspection in an exposure period of the inspection phase so as to obtain image data of the object under inspection. The exposure period includes the first period and the second period.

Abstract: A floating joint and retainer connection device includes a fixed retainer internally defines a receiving space; an adaptor joint having an end extending through the receiving space to an outer side of the fixed retainer and an axially limiting section formed near another end; a fixing element fitted on the adaptor joint and located outside the fixed retainer for limiting the adaptor joint from moving axially while allowing the adaptor joint to displace radially relative to the fixed retainer; a rolling assembly disposed adjoining the fixed retainer; and a spring located in the receiving space and fitted on the adaptor joint with two ends pressed against the axially limiting section and the fixed retainer or the rolling assembly. When the rolling assembly rolls to displace radially relative to the fixed retainer, a radial frictional force produced by a normal force applied by the spring to the fixed retainer is reduced.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.

Abstract: A method includes forming a 2-D semiconductor material layer over a substrate; forming source/drain contacts over source/drain regions of the 2-D semiconductor material layer; and forming a gate structure over a channel region of the 2-D semiconductor material layer. Forming the source/drain contacts includes performing a first deposition process to deposit a first metal layer over the 2-D semiconductor material layer; and after the first deposition process is completed, performing a second deposition process to deposit a second metal layer over the first metal layer, in which the second metal layer has a higher melting point than the first metal layer.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.

Abstract: A hand tool capable of switching operating direction includes: a handgrip (10); an actuating unit (20) having an actuating seat (21) and a positioning set (25), the actuating seat (21) has an accommodating slot (221) and pivotal slots (222), the positioning set (25) has an elastic member (26) and a positioning member (27); a positioning unit (30) having latching members (31) and an elastic unit (32), the latching members (31) is pivotally connected to the pivotal slot (222) and has a latching tooth (331); a switching component (40) having a rotation disk (41) and abutting blocks (42), the rotation disk (41) has positioning slots (43) allowing the positioning member (27) to be mounted; and a rotating rod (50) having a ratchet (52); the positioning member (27) is selectively mounted in one of the positioning slots (27) when the rotation disk (41) is being rotated.

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

Abstract: A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

Abstract: A semiconductor device includes semiconductor nanosheets, a gate structure, and a dielectric spacer. The semiconductor nanosheets are vertically stacked over each other, disposed above a semiconductor substrate, and serve as channel regions. A bottommost semiconductor nanosheet most proximate from the semiconductor substrate is a thinnest nanosheet of the semiconductor nanosheets. The gate structure surrounds each of the semiconductor nanosheets in a first cross-section, and the dielectric spacer is interposed between the bottommost semiconductor nanosheet and the semiconductor substrate and adjoins the gate structure in the first cross-section.

Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.

Abstract: A method includes forming a first, second, third, fourth, fifth, and sixth fin structure. The second fin structure is separated from each of the first and third fin structures by a first distance, the fifth fin structure is separated from each of the fourth and sixth fin structures by the first distance, and the third fin structure is separated from the fourth fin structure by a second distance greater than the first distance. The method includes forming a first dummy gate structure overlaying the first through third fin structures, and a second dummy gate structure overlaying the fourth through sixth fin structures; forming a number of source/drain structures that are coupled to the first, second, third, fourth, fifth, and sixth fin structures, respectively; and replacing the third fin structure with a first dielectric structure, and replacing the fourth fin structure with a second dielectric structure.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a light-curing layer disposed on the sensor chip, a light-permeable layer disposed on the light-curing layer, a shielding layer being ring-shaped and disposed on an inner surface of the light-permeable layer, and a package body that is formed on the substrate. A projection region defined by orthogonally projecting the shielding layer onto a top surface of the sensor chip surrounds a sensing region of the sensor chip. A portion of the shielding layer in contact with the light-curing layer defines a ring-shaped arrangement region that has at last one light-permeable slot. The sensor chip, the light-curing layer, the light-permeable layer, and the shielding layer are embedded in the package body that exposes at least part of the light-permeable layer.

Abstract: A circuit and a method for adjusting a periodic input signal are provided. The circuit includes a duty cycle calibration (DCC) device, a phase adjusting device, and a duty cycle measurement (DCM) device. The DCC device is configured to generate a first signal and a second signal in response to the periodic input signal. The first signal and the second signal have different phases. The phase adjusting device is configured to receive the first signal and the second signal to generate a third signal by combining the first signal and the second signal based on a selection signal. The DCM device is configured to measure and adjust a duty cycle of the third signal so that the selection signal is adjusted to generate a periodic output signal. A frequency of the periodic output signal is twice that of the periodic input signal.