Abstract: The present disclosure describes a method to form a semiconductor device with air inner spacers. The method includes forming a semiconductor structure on a first side of a substrate. The semiconductor structure includes a fin structure having multiple semiconductor layers on the substrate, an epitaxial structure on the substrate and in contact with the multiple semiconductor layers, a gate structure wrapped around the multiple semiconductor layers, and an inner spacer structure between the gate structure and the epitaxial structure. The method further includes removing a portion of the substrate from a second side of the substrate to expose the epitaxial structure and the inner spacer structure, forming an oxide layer on the epitaxial structure on the second side of the substrate, and removing a portion of the inner spacer structure to form an opening. The second side is opposite to the first side of the substrate.

Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.

Abstract: A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.

Abstract: Examples provide new roaming test systems for network deployments that can be implemented remotely using a single physical AP. Examples achieve this elegant system by emulating a physical network deployment using a group of VAPs provisioned on the single physical AP (a VAP may refer to a logical or a virtual AP instance on a physical AP). Each VAP of CAP group may be configured to represent a physical AP of the physical network deployment (such a network deployment may be a prospective deployment or, an actual/set-up deployment). Examples can simulate/emulate a wireless client physically moving between physical APs of the network deployment by varying transmission power associated with each VAP as a function of time in a manner that mirrors how a wireless client would perceive transmission power varying for physical APs of the network deployment (represented by the VAPs) as the wireless client moves across the geographical site of the network deployment.

Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, a fourth repeating unit, and a fifth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), the fourth repeating unit has a structure of Formula (IV), and the fifth repeating unit has a structure of Formula (V), a structure of Formula (VI), or a structure of Formula (VII) ?wherein A1, A2, A3, A4, X1, Z1, R1, R2, R3 and Q are as defined in the specification.

Abstract: A computer system for failing a secure boot in a case tampering event comprises a microcontroller unit (MCU); a trusted platform module (TPM), for generating random bytes for a secure boot of the computer system; a bootloader, for storing information comprising the random bytes in the MCU and at least one hardware of the computer system and performing the secure boot, wherein the TPM is comprised in the bootloader; an operating system (OS), for performing the secure boot; and at least one sensor, coupled to the MCU, for detecting a case tampering event, and transmitting a signal for triggering a deletion of the random bytes, if the case tampering event happens. The MCU performs the operation of deleting the random bytes stored in the MCU and the at least one hardware according to a power supply, in response to the signal.

Abstract: The present disclosure generally relates to a two-dimensional magnetic recording (TDMR) read head. The TDMR read head comprises a first sensor, a second sensor, and a middle shield (MS) disposed between the first and second sensors. The MS comprises a seed layer, an IrMn layer disposed on the seed layer, an insertion layer comprising Ru or CoFe disposed on the IrMn layer, a first NiFe layer having a pinned magnetization, and a cap layer disposed over the first NiFe layer. In one embodiment, the MS further comprises an Ru layer disposed on the first NiFe layer and a second NiFe layer disposed on the Ru layer, the second NiFe layer having a pinned magnetization in a direction antiparallel to the first NiFe layer. The insertion layer comprising Ru decreases an exchange energy of the MS. The insertion layer comprising CoFe increases an exchange energy of the MS.

Abstract: A disclosed semiconductor device includes a package substrate, a first semiconductor die coupled to the package substrate, a package lid attached to the package substrate and covering the semiconductor die, and a thermal interface material located between a top surface of the semiconductor die and an internal surface of the package lid. The semiconductor device may further include a dam formed on the internal surface of the package lid. The dam may constrain the thermal interface material on one or more sides of the first semiconductor die such that the thermal interface material is located within a predetermined volume between the top surface of the first semiconductor die and the internal surface of the package lid during a reflow operation. The package lid may include a metallic material and the dam may include an epoxy material formed as a single continuous structure or may be formed as several disconnected structures.

Abstract: An electrical connector includes a bracket having a plurality of mating frames arranged side by side in a lateral direction and opening forward and plural transition modules inserted forward to be at least partially accommodated in the mating frame, wherein the bracket defines plural heat dissipation grooves each located between two adjacent frames and plural heat dissipation fins each located in a corresponding heat dissipation groove, the heat dissipation groove opening through in a front-rear direction.

Abstract: A hammer tacker is provided, wherein the hammer tacker includes: a main body integrally made of plastic and including two side walls and a top wall, each side wall including an ear portion which includes a stop point, a first position and a second position between two ends of each side wall and the stop point, each side wall being gradually thicker from the first position to the stop point, from the second position to the stop point, and from the top wall to the stop point; and a striking mechanism rotatably connected to the two side walls and swingable to abut against the stop point, including a magazine and a striking member, the magazine being disposed between the two side walls and movable relative to the main body, movably located above the magazine, and being configured to strike a staple out from the magazine.

Abstract: An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. The second time delay circuit further includes a second gate-conductor and a second gate via-connector in direct contact with the second gate-conductor. The second gate-conductor intersects a first-type active region structure and a second-type active region structure in a second area, and wherein at least a portion of the second gate via-connector is atop the second-type active region structure.

Abstract: A synchronizing system includes a phase-locked loop (PLL), first and second network controllers (NCs), a retimer and a processor. The PLL receives a local oscillator (LO) signal, generates and outputs a clock signal and a synchronizing signal. The retimer and the first and second NCs operate according to the clock signal. The first/second NC generates a first/second clock-event signal based on the synchronizing signal. The processor generates a first/second Precision Time Protocol (PTP) signal based on the first/second clock-event signal, and transmits the first/second PTP signal to the first/second NC. The second NC delivers the second PTP signal to first transceivers. The retimer performs retiming on the first PTP signal, and delivers the same to second transceivers. In a master mode, the PLL unit generates the synchronizing signal based on the LO signal and a reference time signal received from a global navigation satellite system (GNSS).

Abstract: A SIL monopulse radar includes a self-injection-locking oscillator (SILO), a transmit antenna, two receive antennas, a hybrid coupler, a first demodulator, a second demodulator and a processor. The transmit antenna transmits the oscillation signal of the SILO to object. The two receive antennas receive a reflected signal from the object as a first echo signal and a second echo signal. The hybrid coupler outputs a difference signal and a sum signal. The difference signal is injected into the SILO. The first demodulator frequency-demodulates the oscillation signal to produce a first demodulated signal. The second demodulator phase-demodulates the sum signal by using the oscillation signal as a reference signal to produce a second demodulated signal. The processor processes the first and second demodulated signals to produce a monopulse ratio signal. The SIL monopulse radar can identify the posture and motion of a human body by analyzing the monopulse ratio signal.

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

Abstract: A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second Ill-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a first fin structure formed over a substrate, and the first fin structure includes a plurality of first nanostructures stacked in a vertical direction. The semiconductor device structure further includes a second fin structure formed over the substrate, and the second fin structure includes a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure further includes a dummy fin structure between the first fin structure and the second fin structure. The dummy fin structure includes a first etching stop layer between a bottom portion and a top portion.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a fin structure protruding from a substrate, wherein the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method includes forming a dummy gate structure across the fin structure. The method includes forming a gate spacer on the sidewall of the dummy gate structure. The method includes removing the dummy gate structure to expose the fin structure. The method includes partially removing the second semiconductor material layers to form concave portions on sidewalls of the second semiconductor material layers. The method includes forming dielectric spacers in the concave portions. The method includes removing the first semiconductor material layers to form gaps. The method includes forming a gate structure in the gaps to wrap around the second semiconductor material layers and the dielectric spacers.

Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. one of the cells which is coupled to one of the first input pads and one of the second input pads is turned on, and a current flowing through the turned-on cell is measured.

Abstract: A wireless communication device includes a casing having a wireless signal penetrating area, an antenna sending a wireless signal through the wireless signal penetrating area, and an electromagnetic lens assembly including a lens barrel and a lens. The lens barrel has a first end and a second end. The first end is closer to the wireless signal penetrating area than the second end. The lens disposed in the lens barrel has an incident surface and an emission surface on an axis of the lens. The incident surface is a flat surface facing the first end. The emission surface is a convex surface and has a curvature, which is not equal to 0, from a perspective of a first axis perpendicular to the axis of the lens, and has a curvature of 0 from a perspective of a second axis perpendicular to the axis of the lens and the first axis.

Abstract: A method of grouping certain cell densities to establish the number and volume of cells appearing in an image input the image into a self-encoder having a preset number of a density grouping models to obtain a preset number of reconstructed images. The image and each reconstructed image are input into a twin network model of the density grouping model corresponding to each reconstructed image, and a first error value is calculated between the image and each reconstructed image. A minimum first error value in the first error value set is determined, and a density range corresponding to the density grouping model corresponding to minimum first error value is taken as the density range. An electronic device and a non-volatile storage medium performing the above-described method are also disclosed.