Patents by Inventor Chih Wang

Chih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Foldable electronic device having foldable display
    Patent number: 11503728
    Abstract: A foldable electronic device includes a first casing, a second casing, a hinge structure and a foldable display. The hinge structure connects the first casing and the second casing, and includes a plurality of supporting blocks, a plurality of first hinge blocks and a plurality of second hinge blocks. The supporting blocks are arranged side by side between the first casing and the second casing. The first hinge blocks and the second hinge blocks are respectively arranged at two sides of the supporting blocks. One of the first hinge blocks connects two of the supporting blocks adjacent to each other. One of the second hinge blocks connects two of the supporting blocks adjacent to each other. The foldable display includes a first bonding portion secured to the first casing, a second bonding portion secured to the second casing and a foldable portion aligned to the hinge structure.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: November 15, 2022
    Assignee: Acer Incorporated
    Inventors: Hui-Ping Sun, Wei-Chih Wang, Chun-Hung Wen, Yu-Cheng Shih, Yen-Chou Chueh, Chi-Tai Ho, Kuan-Lin Chen, Chun-Hsien Chen, Chih-Heng Tsou
  • DEVICES AND METHODS FOR CONTROLLING WAFER UNIFORMITY IN PLASMA-BASED PROCESS
    Publication number: 20220359165
    Abstract: Devices and methods for controlling wafer uniformity in plasma-based process is disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a gas distribution plate (GDP) arranged in the process chamber. The housing comprises: a gas inlet configured to receive a process gas, and a gas outlet configured to expel processed gas. The GDP is configured to distribute the process gas within the process chamber. The GDP has a plurality of holes evenly distributed thereon. The GDP comprises a first zone and a second zone. The first zone is closer to the gas outlet than the second zone. At least one hole in the first zone is closed.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Jr-Sheng CHEN, An-Chi LI, Shi-Che HUANG, Chih-Hsien HSU, Zhi-Hao HUANG, Ming Chih WANG, Yu-Pei CHIANG, Chun Yan CHEN
  • APPARATUS FOR FABRICATING A SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE
    Publication number: 20220359169
    Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including placing a wafer on a chuck, wherein the wafer is surrounded by a focus ring, the focus ring is supported by a first actuator, wherein the first actuator is in a cavity defined by the chuck and the edge ring, wherein the first actuator includes an outer ring disposed in the cavity, a piezoelectric layer apart from a top surface of the cavity, wherein an edge of the piezoelectric layer is fixed by the outer ring, and an inner ring disposed in the chamber at a center portion of the piezoelectric layer, performing plasma etch on a surface of the wafer, and controlling a distance between a gas distribution plate and a top surface of the focus ring to be less than a threshold value by the first actuator.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: KEITH KUANG-KUO KOAI, SHIH-KUO LIU, WEN-CHIH WANG, HSIN-LIANG CHEN
  • Organic electroluminescent materials and devices
    Patent number: 11495749
    Abstract: Compounds containing indolocarbazole compounds of Formula I or Formula II comprising terphenyl groups and compounds of Formula III comprising triazine groups are disclosed in this application. These compounds are useful for application in organic electroluminescent devices.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: November 8, 2022
    Assignee: Universal Display Corporation
    Inventors: Lichang Zeng, Ting-Chih Wang, Zhiqiang Ji, Walter Yeager, Alexey Borisovich Dyatkin, Bin Ma, Chuanjun Xia, Bert Alleyne
  • Interconnect structure with air-gaps
    Patent number: 11495539
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire arranged within an inter-level dielectric (ILD) layer and a second interconnect wire arranged within the ILD layer. A dielectric material continuously extends over the first interconnect wire and the ILD layer. The dielectric material is further disposed between sidewalls of the first interconnect wire and one or more air-gaps arranged along opposing sides of the first interconnect wire. A via is disposed over the second interconnect wire and extends through the dielectric material. A second ILD layer is disposed on the dielectric material and surrounds the via.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
  • Electronic device
    Patent number: 11487331
    Abstract: An electronic device includes a first body, a second body pivoted to the first body and a magnetic force mechanism. The first body includes a driving portion. The second body includes a casing, a flexible display and a supporting mechanism movably disposed in the casing. The flexible display is attached to the supporting mechanism. The magnetic force mechanism is disposed in the casing, wherein a portion of the magnetic force mechanism is exposed from the casing and abuts against the driving portion. The magnetic force mechanism is magnetically coupled to the supporting mechanism, wherein the magnetic force mechanism generates a magnetic attraction force or a magnetic repulsion force to the supporting mechanism by the second body rotating relative to the first body.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: November 1, 2022
    Assignee: Acer Incorporated
    Inventors: Chun-Hung Wen, Wei-Chih Wang, Chi-Tai Ho, Yu-Cheng Shih, Hui-Ping Sun, Chun-Hsien Chen, Kuan-Lin Chen, Chih-Heng Tsou, Yen-Chou Chueh
  • Organic electroluminescent materials and devices
    Patent number: 11485706
    Abstract: A novel composition formed of a first compound is disclosed where the first compound is selected from
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 1, 2022
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Bin Ma, Ting-Chih Wang, Vadim Adamovich
  • WAFER POD TRANSFER ASSEMBLY
    Publication number: 20220344191
    Abstract: A wafer pod transfer assembly is provided. The wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.
    Type: Application
    Filed: July 22, 2021
    Publication date: October 27, 2022
    Inventors: Chih-Wei CHOU, Sheng-Yuan Lin, Yuan-Hsin Chi, Yin-Tun Chou, Hung-Chih Wang, Yu-Chi Liu
  • METHOD FOR FORMING LAYER
    Publication number: 20220344133
    Abstract: A method for forming a layer includes following operations. A workpiece is received in an apparatus for deposition. The apparatus for deposition includes a chamber, a pedestal disposed in the chamber to accommodate the workpiece, and a ring disposed on the pedestal. The ring includes a ring body having a first top surface and a second top surface and a barrier structure disposed between the first top surface and the second top surface. A vertical distance is defined by a top surface of the barrier structure and a top surface of the workpiece. The vertical distance is between approximately 0 mm and approximately 50 mm. A target disposed in the apparatus for deposition is sputtered. A sputtered material is deposited onto a top surface of the workpiece to form a layer. The barrier structure alters an electrical density distribution during the depositing the sputter material.
    Type: Application
    Filed: July 12, 2022
    Publication date: October 27, 2022
    Inventors: HSIN-LIANG CHEN, WEN-CHIH WANG, CHIA-HUNG LIAO, CHENG-CHIEH CHEN, YI-MING YEH, HUNG-TING LIN, YUNG-YAO LEE
  • HEAD-MOUNTED DISPLAY
    Publication number: 20220334398
    Abstract: A head-mounted display includes a display host, a head belt base, a first lateral head belt, a second lateral head belt, an auxiliary head belt, a knob, a first driving component and a second driving component. The head belt base is connected to the display host through the first and second lateral head belts and the auxiliary head belt. The knob is pivoted to the head belt base, and the knob is coupled to the first and second lateral head belts through the first driving component and is coupled to the auxiliary head belt through the second driving component. The knob synchronously drives the first and second driving components, to drive the first and second lateral head belts through the first driving component and drive the auxiliary head belt through the second driving component. Alternatively, the knob drives one of the first driving component and the second driving component.
    Type: Application
    Filed: May 17, 2021
    Publication date: October 20, 2022
    Applicant: Acer Incorporated
    Inventors: Yu-Cheng Shih, Chih-Heng Tsou, Yen-Chou Chueh, Wei-Chih Wang, Hui-Ping Sun, Chun-Hsien Chen
  • System of driving and controlling motor
    Patent number: 11476789
    Abstract: A system of driving and controlling a motor is provided. A main controller adjusts frequencies of all or some of pulse waves of an initial pulse width modulation signal to output a pulse width modulation signal according to instruction information. The adjusted frequency of each of the pulse waves is equal to a first preset frequency or a second preset frequency. When a motor driver drives the motor to stably rotate, the motor driver decodes each of the pulse waves having the first preset frequency into a first message and decodes each of the pulse waves having the second preset frequency into a second message. The motor driver arranges and combines all of the first messages and the second messages that are decoded from the pulse waves to obtain the instruction information. The motor driver executes an operation instructed by the instruction information.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: October 18, 2022
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Yun-Li Liu, Wei-Chih Wang, Yuan-Hung Wang
  • Semiconductor processing station
    Patent number: 11462425
    Abstract: A semiconductor processing station includes first and second chambers, and a cooling stage. The second chamber includes a cooling pipe disposed inside the second chamber, and an external pipe. The cooling pipe includes a first segment disposed along a sidewall of the second chamber, and a second segment disposed perpendicular to the first segment and located above a wafer carrier in the second chamber. An end of the second segment is connected to an end of the first segment. The external pipe is connected to the second segment distal from the end of the second segment to provide a fluid to flow through the cooling pipe from an exterior to an interior of the second chamber. The fluid discharges toward the wafer carrier through the first segment. The first chamber is surrounded by the second chamber and the cooling stage, and communicates between the cooling stage and the second chamber.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: October 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Lu, Hon-Lin Huang, Hung-Chih Wang
  • Additive and application thereof
    Patent number: 11459506
    Abstract: An additive includes an additive molecule having a structure represented by formula (I): wherein R1, A1, A2, Z1, K1, n1, and n2 are defined as in the specification.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: October 4, 2022
    Assignee: DAXIN MATERIALS CORPORATION
    Inventors: Chung-Hsien Wu, Yi-Chun Lin, Chun-Chih Wang
  • Electronic Devices Having Image Transport Layers and Electrical Components
    Publication number: 20220309980
    Abstract: An electronic device may have a display with pixels configured to display an image. The pixels may be overlapped by a cover layer. The display may have peripheral edges with curved cross-sectional profiles. An inactive area in the display may be formed along a peripheral edge of the display or may be surrounded by the pixels. Electrical components such as optical components may be located in the inactive area. An image transport layer may be formed from a coherent fiber bundle or Anderson localization material. The image transport layer may overlap the pixels, may have an opening that overlaps portions of the inactive area, may have an output surface that overlap portions of the inactive area, and/or may convey light associated with optical components in the electronic device.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Inventors: Ying-Chih Wang, Michael J. Brown, Michael B. Wittenberg, Paul C. Kelley, Rasamy Phouthavong, Tyler R. Kakuda, Jean-Pierre S. Guillou, Marwan Rammah
  • Organic electroluminescent materials and devices
    Patent number: 11456423
    Abstract: A composition of materials including a first compound having a structure according to Formula I
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: September 27, 2022
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Lichang Zeng, Suman Layek, Pierre-Luc T. Boudreault, Zeinab Elshenawy, Gregg Kottas, Alexey Borisovich Dyatkin, Scott Joseph, Vadim Adamovich, Chuanjun Xia, Ting-Chih Wang, Walter Yeager
  • POWER ALARM AND FIRE LOADING RISK REDUCTION FOR A DEPOSITION TOOL
    Publication number: 20220301947
    Abstract: A deposition tool includes a power cable pedestal including a pedestal body with a first surface and a second surface and a guide hole that extends through the pedestal body from the first surface to the second surface, where at least a portion of a sidewall of the guide hole has a slanted surface, and where the pedestal body is formed from a first material with a melting point that is higher than a melting point of Polyoxymethylene (POM). The deposition tool includes a bushing arranged over the guide hole, where the bushing is formed from a second material with a melting point that is higher than the melting point of POM.
    Type: Application
    Filed: June 11, 2021
    Publication date: September 22, 2022
    Inventors: Chih-Wei CHOU, Yuan-Hsin CHI, Sheng-Yuan LIN, Yin-Tun CHOU, Hung-Chih WANG, Yu-Chi LIU
  • Apparatus for fabricating a semiconductor structure and method of fabricating a semiconductor structure
    Patent number: 11443923
    Abstract: The present disclosure provides an apparatus for fabricating a semiconductor structure, including a chuck, an edge ring surrounding the chuck, wherein the edge ring comprises a cavity, a focus ring adjacent to an edge of the chuck and over the edge ring, and a first actuator in the cavity of the edge ring and engaging with the focus ring.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Keith Kuang-Kuo Koai, Shih-Kuo Liu, Wen-Chih Wang, Hsin-Liang Chen
  • TRANSMITTER HAVING HARMONIC IMPEDANCE ADJUSTMENT CIRCUIT
    Publication number: 20220286096
    Abstract: The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.
    Type: Application
    Filed: February 7, 2022
    Publication date: September 8, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Ting-Yao Huang, Teng-Yuan Chang, Po-Chih Wang, Ka-Un Chan
  • Electronic devices having image transport layers and electrical components
    Patent number: 11436964
    Abstract: An electronic device may have a display with pixels configured to display an image. The pixels may be overlapped by a cover layer. The display may have peripheral edges with curved cross-sectional profiles. An inactive area in the display may be formed along a peripheral edge of the display or may be surrounded by the pixels. Electrical components such as optical components may be located in the inactive area. An image transport layer may be formed from a coherent fiber bundle or Anderson localization material. The image transport layer may overlap the pixels, may have an opening that overlaps portions of the inactive area, may have an output surface that overlap portions of the inactive area, and/or may convey light associated with optical components in the electronic device.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: September 6, 2022
    Assignee: Apple Inc.
    Inventors: Ying-Chih Wang, Michael J. Brown, Michael B. Wittenberg, Paul C. Kelley, Rasamy Phouthavong, Tyler R. Kakuda, Jean-Pierre S. Guillou, Marwan Rammah
  • PACKAGE STRUCTURE AND METHOD OF FORMING THEREOF
    Publication number: 20220278083
    Abstract: A package structure includes a package substrate, a first die, a second die, a first underfill, and a second underfill. The first die and a second die are disposed on the package substrate. The first underfill is between the first die and the package substrate, and the first underfill includes a first extension portion extending from a first sidewall of the first die toward the second die. The second underfill is between the second die and the package substrate, and the second underfill includes a second extension portion extending from a second sidewall of the second die toward the first die, the second extension portion overlapping the first extension portion on the package substrate.
    Type: Application
    Filed: June 17, 2021
    Publication date: September 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jen-Yuan CHANG, Sheng-Chih WANG