Abstract: A manufacturing method for a recessed access device includes the following operations. A trenching is formed in a substrate. A gate oxide layer is formed within the substrate by oxidizing an inner surface of the trench. A first gate layer is formed in a bottom of the trench, wherein a portion of the gate oxide layer above the first gate layer is exposed from the trench. A second gate layer is formed in the trench to cover the first gate layer and the portion of the gate oxide layer and form a recess over the first gate layer, wherein the second gate layer has a vertical portion covering the portion of the gate oxide layer and a horizontal portion having an upper surface exposed from the recess. An ion implantation is performed to the horizontal portion to form a doped horizontal portion.

Abstract: The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a memory unit including a memory unit conductive layer positioned above the substrate and a lateral oxidized intervention layer positioned below the memory unit conductive layer, and a control unit positioned in the substrate and below the lateral oxidized intervention layer. The lateral oxidized intervention layer includes a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of capacitor contacts positioned over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion; a plurality of bit line contacts positioned over the substrate and a plurality of bit lines positioned over the plurality of bit line contacts, wherein at least one of the plurality of bit line is a wavy line extending between two adjacent capacitor contacts; and a capacitor structure positioned over the head portion.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device can be a recessed access device (RAD) transistor, which includes a substrate, a word line disposed in the substrate and surrounded by a dielectric liner, an isolation layer disposed in the substrate to cap the word line, and an insulative plug penetrating through the isolation layer and extending into the word line.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first semiconductor device, a first conductive layer and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends along a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer.

Abstract: A semiconductor device and a method for detecting cracks are provided. The semiconductor device includes a first conductive layer, a second conductive layer positioned above the first conductive layer, an isolation layer positioned between the first conductive layer and the second conductive layer, and a transistor electrically coupled to the first conductive layer. The first conductive layer, the second conductive layer, the insulating layer, and the transistor together form a crack detecting structure.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of creating at least one trench in a substrate; forming a dielectric film on the substrate in the trench; depositing a first conductive layer on the dielectric film to partially fill the trench; depositing an insulative film on the first conductive layer; depositing a second conductive layer to bury the insulative film; and recessing the first conductive layer, until the insulative film is entirely removed. Due to the deposition of the insulative film on the first conductive layer, the etch depth of the superfluous first conductive layer can be accurately controlled.

Abstract: The present disclosure relates to a power supply device including a voltage conversion circuit, a switching circuit and a control circuit. The voltage conversion circuit is configured to generate a charging signal according to the power supply signal. The switching circuit is electrically connected to the voltage conversion circuit, and is configured to selectively conduct the voltage conversion circuit to a first device or a second device. The control circuit is configured to the switching circuit. When the voltage conversion circuit charges the first device and the charging signal corresponds to a first switching condition, the control circuit controls the switching circuit to disconnect to the voltage conversion circuit and the first device, then controls the switching circuit to connect to the voltage conversion circuit and the second device to charge the second device.

Abstract: The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a memory unit including a memory unit conductive layer positioned above the substrate and a lateral oxidized intervention layer positioned below the memory unit conductive layer, and a control unit positioned in the substrate and below the lateral oxidized intervention layer. The lateral oxidized intervention layer includes a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion.

Abstract: A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided.

Abstract: A pressure measuring method, applied to a pressure measuring apparatus, comprising: measuring a first pressure sensing value when the pressure measuring apparatus operates at a first scan frequency and receives a first pressure; and measuring a second pressure sensing value when the pressure measuring apparatus operates a second scan frequency and receives the first pressure. The first pressure sensing value and the second pressure sensing value are different, and a change between the first pressure sensing value and the second pressure sensing value is according to a change between the first scan frequency and the second scan frequency. The first scan frequency and the second scan frequency are different. The pressure measuring method can further comprise a calibrating mechanism to compensate the sensed pressure. By this way, the pressure sensing value can be calibrated, to solve the issue that the pressure sensing values are affected by scan frequencies.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of capacitor contacts positioned over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion; a plurality of bit line contacts positioned over the substrate and a plurality of bit lines positioned over the plurality of bit line contacts, wherein at least one of the plurality of bit line is a wavy line extending between two adjacent capacitor contacts; and a capacitor structure positioned over the head portion.

Abstract: Various powered wheeled board vehicles are disclosed. In some embodiments, the vehicle includes a deck having a forward portion and a rearward portion. At least one front wheel can be connected with the deck under the forward portion. The front wheel can be configured to swivel about a first axis and rotate about a second axis. A powered wheel can be connected with the rearward portion. In some configurations, the rear wheel comprises a hub motor.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having an upper surface; a plurality of first bit line contacts contacting the upper surface of the substrate; a plurality of first bit lines respectively correspondingly positioned on the plurality of first bit line contacts; a plurality of second bit line contacts contacting the upper surface of the substrate; and a plurality of second bit lines respectively correspondingly positioned on the plurality of first bit line contacts. In some embodiments, the top surfaces of the plurality of second bit line contacts are positioned at a vertical level higher than the top surfaces of the plurality of first bit lines.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having an upper surface; a plurality of first bit line contacts contacting the upper surface of the substrate; a plurality of first bit lines respectively correspondingly positioned on the plurality of first bit line contacts; a plurality of second bit line contacts contacting the upper surface of the substrate; and a plurality of second bit lines respectively correspondingly positioned on the plurality of first bit line contacts. In some embodiments, the top surfaces of the plurality of second bit line contacts are positioned at a vertical level higher than the top surfaces of the plurality of first bit lines.

Abstract: A ride-on vehicle, such as for a child, includes a vehicle body and one or more wheels that support the vehicle body relative to a surface. At least one of the wheels includes a hub motor arrangement that provides a drive torque for propelling the vehicle. The hub motor arrangement includes a housing defining an interior space. An axle or other mounting element(s) define an axis of rotation of the housing. Preferably, the axle or other mounting element(s) do not pass completely through the housing. A motor drives the housing through a transmission. Preferably, the motor is a standard, compact motor that is positioned on the axis of rotation and can be laterally offset from a central plane of the housing. In some embodiments, a traction element is carried directly by the housing.

Abstract: A ride-on vehicle, such as for a child, includes a vehicle body and one or more wheels that support the vehicle body relative to a surface. At least one of the wheels includes a hub motor arrangement that provides a drive torque for propelling the vehicle. The hub motor arrangement includes a housing defining an interior space. An axle or other mounting element(s) define an axis of rotation of the housing. Preferably, the axle or other mounting element(s) do not pass completely through the housing. A motor drives the housing through a transmission. Preferably, the motor is a standard, compact motor that is positioned on the axis of rotation and can be laterally offset from a central plane of the housing. In some embodiments, a traction element is carried directly by the housing.