Abstract: A memory array is disclosed. The memory array includes a plurality of memory cells disposed over a substrate. Each of the memory cells is coupled to a corresponding one of a plurality of word lines and a corresponding one of a plurality of bit line pairs. First four of the memory cells that are coupled to four consecutive ones of the word lines and to a first one of the bit line pairs are abutted to one another on the substrate along a single lateral direction.

Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.

Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.

Abstract: The present application provides a transmission structure of an antenna and a proximity sensing circuit. The transmission structure includes a transmission line and at least one radio-frequency short-circuit element, a first coupling end of the transmission line is coupled to an antenna, and a second coupling end of the transmission line is coupled to a proximity sensing circuit, and the at least one radio-frequency short-circuit element is coupled between the transmission line and a ground, and is located between the antenna and the proximity sensing circuit. Utilizing the at least one radio-frequency short-circuit element in conjunction with the transmission line so that the transmission path between the antenna and the proximity sensing circuit has the high impedance, and hence preventing a radio-frequency signal from the antenna from affecting the sensing accuracy of the proximity sensing circuit.

Abstract: A circuit structure includes a substrate that includes a first transistor stack over the substrate that includes: a first transistor where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type. The structure also includes a plurality of first conductive lines in a first metal layer above the first transistor stack, the plurality of first conductive lines electrically connected to the first transistor stack. The structure also includes a plurality of second conductive lines in a second metal layer below the substrate and underneath the first transistor stack, the plurality of second conductive lines electrically connected to the first transistor stack. The plurality of first conductive lines are configured asymmetrically with respect to the plurality of second conductive lines.

Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

Abstract: A memory cell includes a write bit line, a read word line, a write transistor, and a read transistor. The write transistor is coupled between the write bit line and a first node. The read transistor is coupled to the write transistor by the first node. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor is coupled to the read word line, and a source terminal of the read transistor is coupled to a second node. The write transistor is configured to set a stored data value of the memory cell by a write bit line signal that adjusts a polarization state of the read transistor. The polarization state corresponds to the stored data value.

Abstract: An endoscope system and a wireless controller are provided. The wireless controller includes a handle and a permanent magnet having a non-columnar shape. The handle has a grip portion and a controlling portion that is connected to the grip portion. The permanent magnet is assembled in the controlling portion. The permanent magnet is mirror-symmetrical across a largest cross section thereof. A volume of the permanent magnet gradually decreases from the largest cross section along two opposite directions perpendicular to the largest cross section. The permanent magnet of the wireless controller can generate a magnetic field to control a capsule endoscope located in a biological body from outside of the biological body.

Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.

Abstract: An integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. The first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. The first conductor has a distal edge separated from a first power rail, and the second conductor segment is connected to a second power rail through a via-connector. A distance from the first power rail to a proximal edge of the first conductor segment is larger than a distance from the second power rail to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.

Abstract: A semiconductor device includes a substrate and a first transistor on a first side of the substrate. The semiconductor device further includes a first electrode contacting a first region of the first transistor. The semiconductor device further includes a spacer extending along a sidewall of the first transistor. The semiconductor device further includes a self-aligned interconnect structure (SIS) separated from at least a portion of the first electrode by the spacer, wherein the SIS extends through the substrate. The semiconductor device further includes a second electrode contacting a surface of the first electrode farthest from the substrate, wherein the second electrode directly contacts the SIS.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure that includes a first negative capacitance material, and an isolation structure formed over the substrate. The semiconductor device structure includes a gate structure formed over the fin structure, and a source feature and a drain feature formed over the fin structure. An interface between the fin structure and the source feature is lower than a top surface of the isolation structure.

Abstract: A MIM structure and manufacturing method thereof are provided. The MIM structure includes a substrate and a metallization structure over the substrate. The metallization structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, a top electrode layer on the ferroelectric layer, a first contact electrically coupled to the top electrode layer, and a second contact penetrating the dielectric layer and the ferroelectric layer, electrically coupled to a base portion of the bottom electrode layer. The bottom electrode layer includes the base portion and a plurality of protrusions, each of the protrusions is protruding from the base portion and leveled with a lower surface of the dielectric layer, each portion of the dielectric layer over the bottom electrode layer substantially have identical thicknesses.

Abstract: A tissue repair device and a method for using the same are provided. The tissue repair device includes a body portion and at least one wire. The body portion includes an inner layer and an outer layer. The inner layer is close to a tissue, wherein the inner layer includes a hydrophilic structure, and the outer layer includes a hydrophobic structure. The wire is connected to the body portion to fix the body portion to the tissue.

Abstract: The present disclosure provides an external rotor motor including a rotor, an air guider, a pillow and a stator. The rotor includes a hub. The air guider includes a connecting ring and rotor air-guiding members. The connecting ring is disposed on the hub. The rotor air-guiding members are disposed on the connecting ring. A first gap is formed among any two adjacent rotor air-guiding members and the connecting ring. The pillow includes a stator flange, a cylinder and fins. The stator flange is disposed on the cylinder. The fins are radially arranged on a first surface of the stator flange. A second gap is formed among any two adjacent fins and the stator flange. A first acute angle is formed between a radial extension direction of each of the fins and a first tangent direction of the cylinder. The stator is mounted on the pillow and rotates along an axis.

Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a first oxide material having a first sidewall and a second sidewall, a first spacer layer in contact with the first sidewall of the first oxide material, the first spacer layer having a first conductivity type, a second spacer layer in contact with the second sidewall of the first oxide material, wherein the second spacer layer has the first conductivity type. The memory device also includes a channel layer having a second conductivity type that is opposite to the first conductivity type, wherein the channel layer is in contact with the first oxide material, the first spacer layer, and the second spacer layer. The memory device further includes a ferroelectric layer in contact with the channel layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Abstract: A nucleic acid amplification system and a method thereof. An external energy source is used to drive nanoparticles with a regional thermal transfer to generate an energy response, so that the target nucleic acids on the nanoparticles are subjected to a polymerase chain reaction (PCR) or a nucleic acid isothermal amplification reaction, and the liquid in the reaction space is used for refrigeration to achieve rapid temperature regulation, such that the target nucleic acids accumulated on the surface of the nanoparticles are amplified. The concentration, capture and collection of the nanoparticles can be carried out by means of centrifugation, magnetic capture, lateral flow chromatography, etc. Subsequently, detection can be carried out by means of analyzing the fluorescence intensity and the color change of the layer after amplification.

Abstract: A method of decoding video data by an electronic device is provided. The electronic device receives the video data and determines a block unit from a current frame included in the video data. The electronic device determines, from a plurality of candidate lines, a partitioning line for dividing the block unit into a pair of geometric partitions using a geometric partitioning mode and, from a plurality of candidate modes, two different prediction modes of the block unit to generate two predicted blocks for the pair of the geometric partitions. The electronic device determines a blending width of the partitioning line from a plurality of candidate widths based on a block size of the block unit and weightedly combining the two predicted blocks along the partitioning line based on the blending width to reconstruct the block unit.

Abstract: A semiconductor structure includes: a plurality of calibration reference features disposed on a substrate and spaced apart from each other in a first direction; and a plurality of columns of first active features and a plurality of columns of second active features respectively disposed on opposite sides of the calibration reference features, wherein each of the columns of first active features is spaced apart from each other in a second direction, each of the columns of second active features is spaced apart from each other in the second direction, and the calibration reference features, the first active features, and the second active features are disposed on the same layer and are a portion of the substrate.