Patents by Inventor Chih-Ming Chen

Chih-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12634336
    Abstract: An artificial intelligence frontend system, an artificial intelligence frontend operation method, a computer-readable recording medium with a stored program, and a non-transitory computer program product, where the artificial intelligence frontend operation method includes: executing an external clarification procedure in response to receiving a query by an input frontend to obtain an external clarification query; directing the external clarification query to an input filter element; and executing a filtering procedure by the input frontend on the external clarification query via the input filter element to filter the external clarification query and sending an external clarification query which is filtered to an external chatbot via the input filter element.
    Type: Grant
    Filed: June 7, 2024
    Date of Patent: May 19, 2026
    Assignee: WISTRON CORPORATION
    Inventor: Chih-Ming Chen
  • Publication number: 20260126841
    Abstract: A universal serial bus (USB) power delivery device is provided, including a bit detector, a start of packet (SOP) cycle counter, a reset detector, and a flag generator. The bit detector receives and detects an input data signal, and enables a preamble confirmation signal in response to a preamble byte in the input data signal. The SOP cycle counter starts counting and enables an SOP enable signal in response to the preamble confirmation signal being disabled. The reset detector receives and determines whether the input data signal includes codes related to a hard reset, to output an invalid hard reset signal and a K code confirmation signal. The flag generator receives the SOP enable signal, the invalid hard reset signal, the K code confirmation signal, and a reset enable signal, to output an invalid hard reset flag to an event recorder.
    Type: Application
    Filed: August 13, 2025
    Publication date: May 7, 2026
    Inventor: Chih-Ming CHEN
  • Patent number: 12621606
    Abstract: A control system and a control method for speakers in a field are provided. The control method includes: outputting an audio signal by a first speaker corresponding to a first output power and a second speaker corresponding to a second output power; measuring a first volume and a first time delay corresponding to the audio signal by a first microphone; performing a calculation of an optimization algorithm according to the first output power, the second output power, the first volume, and the first time delay to obtain a first recommended output power corresponding to the first speaker and a second recommended output power corresponding to the second speaker; and configuring the first output power according to the first recommended output power, and configuring the second output power according to the second recommended output power.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: May 5, 2026
    Assignee: Wistron Corporation
    Inventors: Shou-Jung Chang, Chih-Ming Chen, Chun Cheng Li
  • Patent number: 12621003
    Abstract: The preferred embodiment of the present disclosure relates to a decoding method for reducing the influence of noise power signal line and a decoding circuit. The method includes: dividing an analog signal to be decoded into a plurality of levels; performing an edge detection according to the levels to obtain a first edge detection signal; setting the levels which is smaller than a lower level to the lower level and performing the edge detection to obtain the second edge detection signal; setting the levels which is greater than a higher level to the higher level and performing the edge detection to obtain a third edge detection signal; decoding the first, the second, the third edge detection signal to obtain an optimum edge detection signal.
    Type: Grant
    Filed: September 20, 2024
    Date of Patent: May 5, 2026
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chih-Ming Chen, Cheng-Chung Chou
  • Patent number: 12615963
    Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface is configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and is configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: April 28, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Chiao-Chun Hsu, Chung-Yi Yu
  • Patent number: 12609658
    Abstract: A pre-compensation method for a pre-compensation circuit coupled to a power amplifier to compensate for nonlinearity of the power amplifier includes performing pre-distortion according to at least one parameter or at least one hyperparameter to convert a first input signal received by the pre-compensation circuit into a first pre-distortion output signal, updating the at least one parameter or the at least one hyperparameter according to Bayesian Optimization, Causal Bayesian Optimization, or Dynamic Causal Bayesian Optimization, and performing pre-distortion according to the at least one parameter updated or the at least one hyperparameter updated to convert a second input signal received by the pre-compensation circuit into a second pre-distortion output signal.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: April 21, 2026
    Assignee: Wistron Corporation
    Inventor: Chih-Ming Chen
  • Publication number: 20260096346
    Abstract: The present disclosure, in some embodiments, relates to a device structure. The device includes a substrate. A piezoelectric device is disposed over the substrate. The piezoelectric device includes a plurality of layers including a first conductor, a second conductor, a piezoelectric material between the first conductor and the second conductor, and a getter material. The plurality of layers respectively have different widths that monotonically decrease away from the substrate to give the piezoelectric device a pyramidal structure in a cross-sectional view.
    Type: Application
    Filed: December 9, 2025
    Publication date: April 2, 2026
    Inventors: Chih-Ming Chen, Chung-Yi Yu
  • Publication number: 20260094992
    Abstract: A position limiting plug includes a main body and a flexible arm structure. The main body has a stop wall. The flexible arm structure extends from a front side of the main body and outwardly towards a direction away from the stop wall, and is configured to be inserted into a first insertion port of a connector. There is a gap between the flexible arm structure and the main body. A bottom surface of the flexible arm structure has an abutting portion adjacent to the gap, and a bottom end of the abutting portion is lower than a bottom surface of the main body. After a male connector plug is inserted into a second insertion port of the connector, the abutting portion is configured to abut against the male connector plug so as to rotate toward the gap.
    Type: Application
    Filed: August 25, 2025
    Publication date: April 2, 2026
    Inventors: Chih-Ming CHEN, You-Lin SHIH
  • Publication number: 20260068548
    Abstract: The problem of reducing the forming voltage for an RRAM cell is solved with a resistive switching structure having at least two distinct layers. Thicknesses and compositions of the layers are selected so that a difference in oxygen affinity between the layers produces intrinsic oxygen vacancies in one of the layers. The problem of increasing endurance is solved by adding a dopant metal to the lower oxygen affinity layer. The dopant metal has a higher oxygen affinity than the bulk metal of the lower oxygen affinity layer. The lower oxygen affinity layer may have a laminate structure in which the dopant metal is disposed in distinct strata.
    Type: Application
    Filed: December 16, 2024
    Publication date: March 5, 2026
    Inventors: Fa-Shen Jiang, Yi-Yang Wei, Bi-Shen Lee, Chih-Ming Chen, Hai-Dang Trinh
  • Publication number: 20260068541
    Abstract: The problem of reducing forming voltage in an RRAM cell is solved by a resistive switching structure having at least two distinct layers of distinct metal oxides. Thicknesses and compositions of the layers are selected so that a difference in oxygen affinity between the layers produces intrinsic oxygen vacancies in one of the layers. The problem of increasing endurance is solved by adding a dopant metal to the lower oxygen affinity layer. The dopant metal has a higher oxygen affinity than the bulk metal of the lower oxygen affinity layer. The lower oxygen affinity layer may have a laminate structure in which the dopant metal is disposed in distinct strata. The dopant metal may have a concentration gradient within the lower oxygen affinity layer. Having the dopant metal concentration diminish in the direction of the higher oxygen affinity layer can further lower the forming.
    Type: Application
    Filed: January 6, 2025
    Publication date: March 5, 2026
    Inventors: Fa-Shen Jiang, Bi-Shen Lee, Yi-Yang Wei, Chih-Ming Chen, Chung-Yi Yu, Cheng-Yuan Tsai
  • Patent number: 12543112
    Abstract: A distribution method and a distribution unit thereof are provided. The distribution unit for the distribution method is coupled to a network entity cluster. In the distribution method, a first packet is received, and a first network entity is selected from a plurality of network entities of the network entity cluster. A target MAC address of the first packet is rewritten to a MAC address of the first network entity, and the first packet to the first network entity is transmitted. With the distribution method, PDU session migration from a busy or failed network entity to an idle one can be within few seconds to avoid service disruption.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: February 3, 2026
    Assignee: Wistron Corporation
    Inventor: Chih-Ming Chen
  • Patent number: 12534361
    Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: January 27, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Ming Chen, Yuan-Chih Hsieh, Chung-Yi Yu
  • Patent number: 12527223
    Abstract: The present disclosure, in some embodiments, relates to a device. The device includes a first electrode on a substrate, a piezoelectric layer on the first electrode, and a second electrode on the piezoelectric layer. A layer of hydrogen getter material is disposed on the first electrode and is separated from the piezoelectric layer by the first electrode. The layer of hydrogen getter material laterally extends past opposing outermost sidewalls of the first electrode, as viewed in a cross-sectional view.
    Type: Grant
    Filed: April 30, 2024
    Date of Patent: January 13, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Chung-Yi Yu
  • Publication number: 20250389891
    Abstract: A dielectric waveguide structure of a semiconductor photonics device is formed prior to formation of the semiconductor photonics components of the semiconductor photonics device. This enables high-temperature processing techniques to be used to form the dielectric waveguide structure without concern for potential damage that might otherwise be caused to the semiconductor photonics components if the dielectric waveguide were to be formed above the semiconductor photonics components. The use of the high-temperature processing techniques may enable low optical loss to be achieved for the dielectric waveguide structure in that the high-temperature processing techniques may be used to achieve a low hydrogen concentration in the dielectric waveguide structure. The low hydrogen concentration in the dielectric waveguide structure enables higher performance to be achieved for the dielectric waveguide structure, including greater operating efficiency and increased communication bandwidth.
    Type: Application
    Filed: June 20, 2024
    Publication date: December 25, 2025
    Inventors: Eugene I-Chun CHEN, Chih-Ming CHEN, De-Yang CHIOU, Chia-Shiung TSAI, Chih-Tsung SHIH, Chia-Hua CHU, Tzu-Heng WU
  • Publication number: 20250366221
    Abstract: A stacked (or vertically arranged) photodetector having at least one contact region on a germanium sensing region. Including the at least one contact on the germanium sensing region reduces the amount of surface area of the germanium sensing region that is interfaced with a substrate (e.g., a silicon substrate) in which the germanium sensing region is included. This reduces the amount of lattice mismatch reduces the amount of misfit defects for the germanium sensing region, which reduces the dark current for the photodetector. The reduced amount of dark current may increase the photosensitivity of the photodetector, may increase low-light performance of the photodetector, and/or may decrease noise and other defects in images and/or light captured by the photodetector, among other examples.
    Type: Application
    Filed: August 7, 2025
    Publication date: November 27, 2025
    Inventors: Chen-Hao CHIANG, Chih-Ming CHEN, Jing-Hwang YANG
  • Patent number: 12456411
    Abstract: An image display method, comprising: setting multiple first driving voltages on a first row of multiple pixel units according to a first driving signal by a driving circuit and multiple data registers; and setting multiple second driving voltages on a second row of the pixel units according to a second driving signal by the driving circuit and the data registers. Wherein setting the second driving voltages of the second row of the pixel units comprises: when one of the second driving voltages is equal to one of the first driving voltages, and both correspond to the same one of the data registers, disabling an input terminal of the same one of the data registers, so that the same one of the data registers maintains one of the first driving voltages as one of the second driving voltages.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: October 28, 2025
    Assignee: AUO CORPORATION
    Inventors: Yu-Jung Huang, Zuei-Tien Chao, Chih-Ming Chen
  • Patent number: 12455298
    Abstract: A test system, for testing a plurality of semiconductor devices, includes a carrying apparatus, an abutting apparatus and a pressing apparatus including a cover and a seat. The cover and the seat constitute a test chamber and a sealed auxiliary chamber. The carrying apparatus is disposed within the test chamber. Each semiconductor device is carried by one of a plurality of test sockets of the carrying apparatus. The abutting apparatus is disposed between the cover and the test sockets. The auxiliary chamber is extracted through at least one extraction hole, such that an air pressure in the auxiliary chamber is lowered to actuate the cover toward the seat and further to apply force to the abutting apparatus, and such that the abutting apparatus presses against the test sockets and the semiconductor devices to allow each test socket to electrically contact with the semiconductor device carried by said one test socket.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: October 28, 2025
    Assignee: TAIWAN MASK CORPORATION
    Inventors: Chih-Ming Chen, Chih-Kang Toh
  • Publication number: 20250323665
    Abstract: The preferred embodiment of the present disclosure relates to a decoding method for reducing the influence of noise power signal line and a decoding circuit. The method includes: dividing an analog signal to be decoded into a plurality of levels; performing an edge detection according to the levels to obtain a first edge detection signal; setting the levels which is smaller than a lower level to the lower level and performing the edge detection to obtain the second edge detection signal; setting the levels which is greater than a higher level to the higher level and performing the edge detection to obtain a third edge detection signal; decoding the first, the second, the third edge detection signal to obtain an optimum edge detection signal.
    Type: Application
    Filed: September 20, 2024
    Publication date: October 16, 2025
    Inventors: Chih-Ming CHEN, Cheng-Chung CHOU
  • Publication number: 20250317693
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a pad barrier layer caps a pad of a piezoelectric device. The pad barrier layer is configured to block hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer. Absent the pad barrier layer, hydrogen ions from hydrogen-ion containing processes performed after forming the pad may diffuse to the piezoelectric layer along a via extending from the pad to the piezoelectric device. By blocking diffusion of hydrogen ions and/or other errant materials to the piezoelectric device, the pad barrier layer may prevent delamination and breakdown of the piezoelectric layer. Hence, the pad barrier layer may prevent failure of the piezoelectric device.
    Type: Application
    Filed: June 18, 2025
    Publication date: October 9, 2025
    Inventor: Chih-Ming Chen
  • Publication number: 20250317471
    Abstract: An artificial intelligence frontend system, an artificial intelligence frontend operation method, a computer-readable recording medium with a stored program, and a non-transitory computer program product, where the artificial intelligence frontend operation method includes: executing an external clarification procedure in response to receiving a query by an input frontend to obtain an external clarification query; directing the external clarification query to an input filter element; and executing a filtering procedure by the input frontend on the external clarification query via the input filter element to filter the external clarification query and sending an external clarification query which is filtered to an external chatbot via the input filter element.
    Type: Application
    Filed: June 7, 2024
    Publication date: October 9, 2025
    Inventor: Chih-Ming CHEN