Abstract: A plan optimization method, a computing apparatus for optimizing the plan, and a computer-readable medium are provided. Obtain multiple medical variables at the current time, at least one of the medical variables is different from the medical variables at the previous time, and one of those medical variables at the current time corresponds to a previous state at the previous time. By inputting those medical variables at the current time into the machine learning model, plan information is determined, where the plan information includes at least one subplan information, and each piece of subplan information corresponds to at least one treatment manner record at a subsequent time. Therefore, it could improve the inference accuracy of the model.

Abstract: A method for reducing influence of noise on a signal line, a decoding circuit and a power provider are disclosed. The method includes steps of: dividing an analog signal to be decoded into levels; determining the level of the analog signal and acquiring the current level of the analog signal to be decoded to obtain a current level number; updating a highest level variable when the current level number is greater than the highest level variable; updating a lowest level variable when the current level number is smaller than the lowest level variable; and outputting an edge detection pulse and setting the highest level variable and the lowest level variable equal to the current level number when the difference between the highest level variable and the lowest level variable is greater than a noise tolerance value.

Abstract: A photonic integrated circuit of a semiconductor device includes a coupling waveguide that has a variable thickness between an edge coupler waveguide and a waveguide of another photonic component of the photonic integrated circuit. In particular, a thickness of the coupling waveguide at the first end of the coupling waveguide facing the edge coupler waveguide is less than a thickness of the coupling waveguide at a second end of the coupling waveguide facing the waveguide of the other photonic component. The thickness of the coupling waveguide may transition between the first end and the second end in an approximately linear manner (e.g., the coupling waveguide is tapered between the first end and the second end), in a curved manner (e.g., the coupling waveguide may have a non-linear transition between the first end and the second end), and/or in another manner.

Abstract: An electronic device includes a logic controller, a time digital converter, and a clock adjustment circuit. The logic controller receives a clock signal and generates a first signal and a second signal according to the clock signal. The first signal leads the second signal by a first time difference. The time digital converter includes a plurality of delay circuits, receives the first signal and the second signal, and enables the second signal to catch up with the first signal in a second time difference through the delay circuits. The clock adjustment circuit adjusts the frequency of the clock signal according to the sum of the first time difference and the second time difference respectively calculated in the previous and subsequent periods of the clock signal.

Abstract: A method for manufacturing a semiconductor device includes: forming a first waveguide structure and a second waveguide structure on a substrate in which the first waveguide structure and the second waveguide structure is spaced apart from each other by a recess; conformally forming an un-doped dielectric layer to cover the first and second waveguide structures and to form a gap between two corresponding portions of the un-doped dielectric layer laterally covering the first waveguide structure and the second waveguide structure, respectively; and forming a doped filling layer to fill the gap.

Abstract: A semiconductor photonics device may include a photonic integrated circuit and may be coupled with an output optical fiber at a top surface of the semiconductor photonics device. To facilitate coupling of modulated optical signals to the output optical fiber at the top surface of the semiconductor photonics device, the semiconductor photonics device may include a mirror structure that is supported by a semiconductor support structure included in the semiconductor photonics device. The mirror structure may be positioned at an angle relative to a surface of a semiconductor substrate of the semiconductor photonics device, which enables the mirror structure to transfer a modulated optical signal propagating in a first direction to a second direction toward the output optical fiber.

Abstract: A method for determining a quantity corresponding to peripheral modules for reducing gate count, executed in a development stage of a SoC, and the method has steps: (A) selecting an estimated quantity corresponding to first peripheral modules; (B) dispose the first peripheral module in the SoC based on the estimated quantity corresponding to first peripheral modules; (C) obtaining an activation status and a peripheral setting parameter and performance parameter set of each of the first peripheral modules; (D) using a trained machine learning model to calculate a first processing timing of data transmission of each of the first peripheral modules based on the activation status and the peripheral setting parameter and performance parameter set of each of the first peripheral modules; (E) using an inference unit to determine whether to reduce the estimated quantity based on the first processing timing of data transmission of each of the first peripheral modules.

Abstract: An artificial intelligence frontend system, an artificial intelligence frontend operation method, a computer-readable recording medium with a stored program, and a non-transitory computer program product, where the artificial intelligence frontend operation method includes: executing an external clarification procedure in response to receiving a query by an input frontend to obtain an external clarification query; directing the external clarification query to an input filter element; and executing a filtering procedure by the input frontend on the external clarification query via the input filter element to filter the external clarification query and sending an external clarification query which is filtered to an external chatbot via the input filter element.

Abstract: A universal serial bus (USB) power delivery device is provided, including a bit detector, a start of packet (SOP) cycle counter, a reset detector, and a flag generator. The bit detector receives and detects an input data signal, and enables a preamble confirmation signal in response to a preamble byte in the input data signal. The SOP cycle counter starts counting and enables an SOP enable signal in response to the preamble confirmation signal being disabled. The reset detector receives and determines whether the input data signal includes codes related to a hard reset, to output an invalid hard reset signal and a K code confirmation signal. The flag generator receives the SOP enable signal, the invalid hard reset signal, the K code confirmation signal, and a reset enable signal, to output an invalid hard reset flag to an event recorder.

Abstract: A control system and a control method for speakers in a field are provided. The control method includes: outputting an audio signal by a first speaker corresponding to a first output power and a second speaker corresponding to a second output power; measuring a first volume and a first time delay corresponding to the audio signal by a first microphone; performing a calculation of an optimization algorithm according to the first output power, the second output power, the first volume, and the first time delay to obtain a first recommended output power corresponding to the first speaker and a second recommended output power corresponding to the second speaker; and configuring the first output power according to the first recommended output power, and configuring the second output power according to the second recommended output power.

Abstract: The preferred embodiment of the present disclosure relates to a decoding method for reducing the influence of noise power signal line and a decoding circuit. The method includes: dividing an analog signal to be decoded into a plurality of levels; performing an edge detection according to the levels to obtain a first edge detection signal; setting the levels which is smaller than a lower level to the lower level and performing the edge detection to obtain the second edge detection signal; setting the levels which is greater than a higher level to the higher level and performing the edge detection to obtain a third edge detection signal; decoding the first, the second, the third edge detection signal to obtain an optimum edge detection signal.

Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface is configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and is configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.

Abstract: A pre-compensation method for a pre-compensation circuit coupled to a power amplifier to compensate for nonlinearity of the power amplifier includes performing pre-distortion according to at least one parameter or at least one hyperparameter to convert a first input signal received by the pre-compensation circuit into a first pre-distortion output signal, updating the at least one parameter or the at least one hyperparameter according to Bayesian Optimization, Causal Bayesian Optimization, or Dynamic Causal Bayesian Optimization, and performing pre-distortion according to the at least one parameter updated or the at least one hyperparameter updated to convert a second input signal received by the pre-compensation circuit into a second pre-distortion output signal.

Abstract: The present disclosure, in some embodiments, relates to a device structure. The device includes a substrate. A piezoelectric device is disposed over the substrate. The piezoelectric device includes a plurality of layers including a first conductor, a second conductor, a piezoelectric material between the first conductor and the second conductor, and a getter material. The plurality of layers respectively have different widths that monotonically decrease away from the substrate to give the piezoelectric device a pyramidal structure in a cross-sectional view.

Abstract: A position limiting plug includes a main body and a flexible arm structure. The main body has a stop wall. The flexible arm structure extends from a front side of the main body and outwardly towards a direction away from the stop wall, and is configured to be inserted into a first insertion port of a connector. There is a gap between the flexible arm structure and the main body. A bottom surface of the flexible arm structure has an abutting portion adjacent to the gap, and a bottom end of the abutting portion is lower than a bottom surface of the main body. After a male connector plug is inserted into a second insertion port of the connector, the abutting portion is configured to abut against the male connector plug so as to rotate toward the gap.

Abstract: The problem of reducing the forming voltage for an RRAM cell is solved with a resistive switching structure having at least two distinct layers. Thicknesses and compositions of the layers are selected so that a difference in oxygen affinity between the layers produces intrinsic oxygen vacancies in one of the layers. The problem of increasing endurance is solved by adding a dopant metal to the lower oxygen affinity layer. The dopant metal has a higher oxygen affinity than the bulk metal of the lower oxygen affinity layer. The lower oxygen affinity layer may have a laminate structure in which the dopant metal is disposed in distinct strata.

Abstract: The problem of reducing forming voltage in an RRAM cell is solved by a resistive switching structure having at least two distinct layers of distinct metal oxides. Thicknesses and compositions of the layers are selected so that a difference in oxygen affinity between the layers produces intrinsic oxygen vacancies in one of the layers. The problem of increasing endurance is solved by adding a dopant metal to the lower oxygen affinity layer. The dopant metal has a higher oxygen affinity than the bulk metal of the lower oxygen affinity layer. The lower oxygen affinity layer may have a laminate structure in which the dopant metal is disposed in distinct strata. The dopant metal may have a concentration gradient within the lower oxygen affinity layer. Having the dopant metal concentration diminish in the direction of the higher oxygen affinity layer can further lower the forming.

Abstract: A distribution method and a distribution unit thereof are provided. The distribution unit for the distribution method is coupled to a network entity cluster. In the distribution method, a first packet is received, and a first network entity is selected from a plurality of network entities of the network entity cluster. A target MAC address of the first packet is rewritten to a MAC address of the first network entity, and the first packet to the first network entity is transmitted. With the distribution method, PDU session migration from a busy or failed network entity to an idle one can be within few seconds to avoid service disruption.

Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

Abstract: The present disclosure, in some embodiments, relates to a device. The device includes a first electrode on a substrate, a piezoelectric layer on the first electrode, and a second electrode on the piezoelectric layer. A layer of hydrogen getter material is disposed on the first electrode and is separated from the piezoelectric layer by the first electrode. The layer of hydrogen getter material laterally extends past opposing outermost sidewalls of the first electrode, as viewed in a cross-sectional view.