Patents by Inventor Chin CHIU
Chin CHIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978703Abstract: A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.Type: GrantFiled: November 17, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ya-Chin Chiu, Ming-Hsien Lin, Chia-Tung Hsu, Lun-Chieh Chiu
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Publication number: 20240144717Abstract: Disclosed are systems, apparatuses, processes, and computer-readable media to capture images. A method of processing image data includes determining a first region of interest (ROI) in an image. The first ROI is associated with a first object. The method can include determining one or more image characteristics of the first ROI. The method can further include determining whether to perform an upsampling process on image data in the first ROI based on the one or more image characteristics of the first ROI.Type: ApplicationFiled: October 26, 2022Publication date: May 2, 2024Inventors: Wen-Chun FENG, Kai LIU, Su-Chin CHIU, Chung-Yan CHIH, Yu-Ren LAI
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Patent number: 11961833Abstract: A high voltage device is used as a lower switch in a power stage of a switching regulator. The high voltage device includes at least one lateral diffused metal oxide semiconductor (LDMOS) device, a first isolation region, a second isolation region, a third isolation region, and a current limiting device. The first isolation region is located in a semiconductor layer, and encloses the LDMOS device. The second isolation region has a first conductivity type, and encloses the first isolation region in the semiconductor layer. The third isolation region has a second conductivity type, and encloses the second isolation region in the semiconductor layer. The current limiting device is electrically connected to the second isolation region, and is configured to operably suppress a parasitic silicon controlled rectifier (SCR) from being turned on.Type: GrantFiled: March 23, 2022Date of Patent: April 16, 2024Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Kuo-Chin Chiu, Chien-Wei Chiu
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Patent number: 11956651Abstract: A system for simulating a wireless communication network over a wired network may comprise a plurality of physical UEs, one or more RANs, and a channel condition emulator. The plurality of UEs may be coupled to one another through the wired network. The one or more RANs may be simulated in software to simulate data transmissions between the plurality of UEs. The channel condition emulator may be simulated in software to derive channel conditions for each of the plurality of UEs based on their current location. The channel condition emulator may further provide the channel conditions to the plurality of UEs and the one or more RANs.Type: GrantFiled: July 13, 2022Date of Patent: April 9, 2024Assignee: Verizon Patent and Licensing Inc.Inventors: Mourad B. Takla, Chin Chiu
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Patent number: 11935957Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: GrantFiled: August 9, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Publication number: 20240069583Abstract: A control circuit including a storage circuit, a voltage detection circuit, a processing circuit, and a wake-up circuit is provided. The storage circuit includes a register and stores a program code. The voltage detection circuit detects an external voltage. The processing circuit accesses the register in response to the external voltage reaching a first predetermined voltage. The processing circuit enters a power-down mode in response to the external voltage reaching a second predetermined voltage. In the power-down mode, the processing circuit stops accessing the register. The wake-up circuit determines whether a wake-up event occurs. In response to the wake-up event, the wake-up circuit directs the processing circuit to exit the power-down mode and enter an operation mode. In response to there being no wake-up event, the processing circuit stays in the power-down mode. In the operation mode, the processing circuit executes the program code.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Chieh-Sheng TU, Te-Tsoung TSAI, Ta-Chin CHIU
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Patent number: 11908800Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.Type: GrantFiled: July 22, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ya-Chin Chiu, Ming-Hsien Lin, Chia-Tung Hsu, Lun-Chieh Chiu
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Publication number: 20240056928Abstract: A method, a network device, and a non-transitory computer-readable storage medium are described in relation to an handover management service. The handover management service may include receiving a measurement report from an end device. The measurement report may include an SINR value in combination with RSRP and/or RSRQ values. The measurement report may include values from a source cell, a candidate target cell, or both source and candidate target cells. The handover management service may determine whether to perform a handover, based on the measurement report in which a handover criteria does not include an RSRQ value. The handover management service may also determine whether to perform a handover based on handover criteria that includes a variable value for a threshold value. The variable value, among values, may be selected and correlated to a value included in the measurement report.Type: ApplicationFiled: August 11, 2022Publication date: February 15, 2024Inventors: Chin Chiu, Chokri Trabelsi, Anil Babu Vontikommu, Asif Dawoodi Gandhi
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Publication number: 20240045826Abstract: A micro controller unit coupled between a master device and a slave device and including a first communication interface, a serial peripheral interface (SPI) circuit, a switch circuit, a second communication interface, and a switching control circuit is provided. The first communication interface receives a first external signal provided by the master device. The SPI circuit is configured to generate an internal signal. The switch circuit uses a second external signal or the internal signal as an output signal according to a control signal. The second communication interface provides the output signal to the slave device. The switching control circuit generates the control signal according to the level of the first external signal.Type: ApplicationFiled: May 18, 2023Publication date: February 8, 2024Inventors: Chieh-Sheng TU, Ta-Chin CHIU
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Publication number: 20240040565Abstract: New Radio (NR)-aware LTE scheduling is provided. An access station for a radio access network includes a first scheduling function. The first scheduling function identifies a User Equipment (UE) device that has a first active wireless connection and a second active wireless connection to the radio access network. The first scheduling function determines that expanded coverage is needed for an uplink transmission for the second active wireless connection and obtains uplink scheduling information for the second active wireless connection. The first scheduling function adjusts uplink scheduling for the first active wireless connection such that power sharing is prioritized for uplink time intervals of the second active wireless connection over overlapping uplink time intervals of the first active wireless connection.Type: ApplicationFiled: October 16, 2023Publication date: February 1, 2024Inventors: Alpaslan Gence Savas, Mathew Thomas, Sachin Vargantwar, Chin Chiu, Maulik Shah
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Publication number: 20240028807Abstract: An embodiment of the present disclosure provides an online integrated microcontroller development tool system. Through the present disclosure, a microcontroller block of a suitable model number is selected according to a client requirement, pins of the microcontroller may be arranged, the microcontroller block with the arranged have been pins is connected to a functional component selected by the client, a corresponding circuit structure is generated, and based on the circuit structure, a microcontroller system hardware description code is generated and output. Different from the conventional development platform, the present disclosure helps clients to develop microcontroller application circuits for different applications through a pin required module, a functional component module and a description code project output module. Thus, purposes of simple operation and saving development time can be achieved.Type: ApplicationFiled: January 10, 2023Publication date: January 25, 2024Inventors: CHIEH-SHENG TU, TA-CHIN CHIU, CHUN-MING HUANG, JEN-CHIH LIU
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Patent number: 11818710Abstract: New Radio (NR)-aware LTE scheduling is provided. An access station for a radio access network includes a first scheduling function. The first scheduling function identifies a User Equipment (UE) device that has a first active wireless connection and a second active wireless connection to the radio access network. The first scheduling function determines that expanded coverage is need for an uplink transmission for the second active wireless connection and obtains uplink scheduling information for the second active wireless connection. The first scheduling function adjusts uplink scheduling for the first active wireless connection such that power sharing is prioritized for uplink time intervals of the second active wireless connection over overlapping uplink time intervals of the first active wireless connection.Type: GrantFiled: September 15, 2021Date of Patent: November 14, 2023Assignee: Verizon Patent and Licensing Inc.Inventors: Alpaslan Gence Savas, Mathew Thomas, Sachin Vargantwar, Chin Chiu, Maulik Shah
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Patent number: 11812456Abstract: The disclosed embodiments are directed toward improvements in dynamic spectrum sharing (DSS) between cellular network technologies. In one embodiment, a method is disclosed comprising initiating scheduling for a resource in a slot and determining a neighboring base station associated with user equipment (UE). The method then determines a type of interference associated with the neighboring base station and the slot and identifies an outer loop link adaptation (OLLA) value associated with the type of interference. An effective data rate is calculated based on the OLLA value and the method completes scheduling using the effective data rate.Type: GrantFiled: January 26, 2021Date of Patent: November 7, 2023Assignee: Verizon Patent and Licensing Inc.Inventors: Jack Anthony Smith, Chin Chiu, Mark E. Newbury, Sachin Vargantwar
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Publication number: 20230345336Abstract: A system described herein may receive respective measures of load associated with first and second cells of a wireless network. The system may receive a measures of utilization associated with the first and second cells, as determined by a User Equipment (“UE”) that is connected to the first cell. The system may determine whether the UE should be handed over from the first cell to the second cell, and further based on the measures of load associated with the first and second cells, the measures of utilization associated with the first and second cells, as determined by the UE. The system may cause the UE to be handed over from the first cell to the second cell based on the determining.Type: ApplicationFiled: April 25, 2022Publication date: October 26, 2023Applicant: Verizon Patent and Licensing Inc.Inventors: Chin Chiu, Md Abu Sayem Sarker, Marcus W. Maples, Abhishek Shah, Asif Dawoodi Gandhi
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Patent number: 11784237Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a gate, a strained layer and a passivation layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate is disposed on the barrier layer. The strained layer is disposed on the barrier layer. The passivation layer covers the gate and the strained layer. The material of the passivation layer differs from that of the strained layer.Type: GrantFiled: December 20, 2019Date of Patent: October 10, 2023Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Kingyuen Wong, Han-Chin Chiu, Ming-Hong Chang, Chunhua Zhou, Jinhan Zhang
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Publication number: 20230315824Abstract: A computer-implemented method for managing operation of an application includes: authenticating a user of the application or a user device associated with a user of the application; and establishing a session with the application and enabling access to the application for the user if the user or the user device is authenticated. The method further includes determining, after the user or the user device is authenticated, whether the user or the user device is or remains present. The method further includes maintaining the session and the enabling of access to the application if it is determined that the user or the user device is or remains present; and terminating the session and disabling access to the application if it is determined that the user or the user device is absent for a predetermined duration.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Kwong Yeung Simon Wong, Chi Hung Tong, Chin Chiu Chung, Sze Man Tong, Chun On Wong
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Publication number: 20230319401Abstract: Disclosed are systems, apparatuses, processes, and computer-readable media to capture images with subjects at different depths of fields. A method of processing image data includes determining, based on a depth map of a previously captured image, a first distance to a first object and a second distance to a second object; identifying a focal point of a camera lens at least in part using the first distance and the second distance; capturing an image using the focal point as a basis for the capture, the image including a first region corresponding to the first object and a second region corresponding to the second object; and generating a second image from the image at least in part by enhancing at least one of the first region or the second region using a point spread function (PSF).Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Wen-Chun FENG, Su-Chin CHIU, Yu-Ren LAI, Hang-Wei LIAW, Jian-Jia SU
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Publication number: 20230316004Abstract: A computer-implemented method for training a natural language translation model. The computer-implemented method includes: processing one or more sets of electronic parallel documents to obtain a plurality of aligned parallel sentences; creating a first training set including a subset of the plurality of aligned parallel sentences; and training the natural language translation model in a first stage using the first training set. The computer-implemented method further includes: modifying the first training set based on translation errors detected after the first stage of training; creating a second training set based on the modified first training set and at least some of the plurality of aligned parallel sentences not in the first training set; and training the natural language translation model in a second stage using the second training set so as to improve translation performance of the natural language translation model.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Kwong Yeung Simon Wong, Chun On Wong, Chin Chiu Chung, Sze Man Tong, Chi Hung Tong
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Patent number: 11776934Abstract: A semiconductor apparatus includes a channel layer, a barrier layer, a source contact and a drain contact, a first doped group III-V semiconductor, a group III-V semiconductor, and a second doped group III-V semiconductor. The barrier layer is disposed on the channel layer. The source contact and the drain contact are disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the first doped group III-V semiconductor and between the source contact and the drain contact. The second doped group III-V semiconductor is disposed on the group III-V semiconductor and between the source contact and the drain contact. The group III-V semiconductor has a central region covered by the second doped group III-V semiconductor and a peripheral region free from coverage by the second doped group III-V semiconductor.Type: GrantFiled: May 23, 2022Date of Patent: October 3, 2023Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventor: Han-Chin Chiu
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Patent number: 11764769Abstract: A control circuit and method for detecting a glitch signal on a bus are provided. The control circuit includes: input ends, respectively receiving a data signal and a clock signal from the bus; a counter, for calculating a time or a number of times in a low level period of the clock signal; a comparator, receiving an output of the time counted by the counter and a threshold value, and generating a comparison result by comparing the time and the threshold value; and an error detector, coupled to the comparator to receive the comparison result, and generating an error flag. When the comparison result indicates that there is a level change during the low level period of the clock signal, the error detector generates an error flag.Type: GrantFiled: July 7, 2022Date of Patent: September 19, 2023Assignee: Nuvoton Technology CorporationInventors: Ta-Chin Chiu, Chieh-Sheng Tu