Abstract: The disclosed embodiments are directed toward improvements in dynamic spectrum sharing (DSS) between cellular network technologies. In one embodiment, a method is disclosed comprising initiating scheduling for a resource in a slot and determining a neighboring base station associated with user equipment (UE). The method then determines a type of interference associated with the neighboring base station and the slot and identifies an outer loop link adaptation (OLLA) value associated with the type of interference. An effective data rate is calculated based on the OLLA value and the method completes scheduling using the effective data rate.

Abstract: A high voltage device includes: a semiconductor layer, a well region, a shallow trench isolation region, a drift oxide region, a body region, a gate, a source, and a drain. The drift oxide region is located on a drift region. The shallow trench isolation region is located below the drift oxide region. A part of the drift oxide region is located vertically above a part of the shallow trench isolation region and is in contact with the shallow trench isolation region. The shallow trench isolation region is formed between the drain and the body region.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A semiconductor apparatus and a fabrication method thereof are disclosed. The semiconductor apparatus includes a substrate, a channel layer, a barrier layer, and a gate structure, and includes: a first doped group III-V semiconductor, a group III-V semiconductor, and a conductor. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the doped group III-V semiconductor. The conductor is disposed on the group III-V semiconductor, where a width of the first doped group III-V semiconductor is greater than a width of the conductor.

Abstract: A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.

Abstract: A system for simulating a wireless communication network over a wired network may comprise a plurality of physical UEs, one or more RANs, and a channel condition emulator. The plurality of UEs may be coupled to one another through the wired network. The one or more RANs may be simulated in software to simulate data transmissions between the plurality of UEs. The channel condition emulator may be simulated in software to derive channel conditions for each of the plurality of UEs based on their current location. The channel condition emulator may further provide the channel conditions to the plurality of UEs and the one or more RANs.

Abstract: A method of deploying cloud services quickly is to make a near-end apparatus be connected to a cloud virtual machine of a cloud server, establish a cloud agent module in the cloud virtual machine, continuously synchronize local data from the near-end apparatus to the cloud virtual machine and converse the local data into cloud structured data, upload local data flow task from the near-end apparatus to the cloud virtual machine for configuring cloud task program. A cloud execution result based on the cloud task program and the cloud structured data corresponds to a local execution result based on the local data and the local data flow task.

Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer above the substrate, a semiconductor stack disposed on and in contact with the first nitride semiconductor layer, and a first electrode in contact with the semiconductor stack. Wherein the semiconductor stack comprises a first layer and a second layer, and a lattice constant of the first layer along an a-axis is less than the second layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a transistor and a heat dissipation structure. The substrate includes first and second semiconductor layers, and includes an insulating layer disposed between the first and second semiconductor layers. The substrate has a recess extending into the insulating layer from a surface of the first semiconductor layer. The transistor includes a hetero-junction structure, a gate electrode, a drain electrode and a source electrode. The hetero-junction structure is disposed on the second semiconductor layer. The gate, drain and source electrodes are disposed over the hetero-junction structure. The gate electrode is located between the drain electrode and the source electrode, and an active area of the hetero-junction structure located between the drain electrode and the source electrode is overlapped with the recess of the substrate.

Abstract: An access control system comprising a first detector, a second detector, and a processor. The first detector is operable to detect presence of a subject in proximity of the access control system. The second detector operable to detect an object identifier associated with an object carried by the subject in proximity of the access control system. The processor is operably connected with the first detector and the second detector. The processor is operable to receive, from the first detector, a first signal indicative of the detection of the presence of the subject, and receive, from the second detector, a second signal containing the detected object identifier. During operation, the processor is arranged to determine that an access event has occurred when it receives both the first signal and the second signal.

Abstract: A semiconductor apparatus and a fabrication method thereof are disclosed. The semiconductor apparatus includes a substrate, a channel layer, a barrier layer, and a gate structure, and includes: a first doped group III-V semiconductor, a group III-V semiconductor, and a conductor. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the doped group III-V semiconductor. The conductor is disposed on the group III-V semiconductor, where a width of the first doped group III-V semiconductor is greater than a width of the conductor.

Abstract: A method of deploying cloud services quickly is to make a near-end apparatus be connected to a cloud virtual machine of a cloud server, establish a cloud agent module in the cloud virtual machine, continuously synchronize local data from the near-end apparatus to the cloud virtual machine and converse the local data into cloud structured data, upload local data flow task from the near-end apparatus to the cloud virtual machine for configuring cloud task program. A cloud execution result based on the cloud task program and the cloud structured data corresponds to a local execution result based on the local data and the local data flow task.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device includes an electron supply layer that is disposed over an upper surface of a semiconductor material and that is laterally arranged between a first conductive terminal and a second conductive terminal. A III-N(III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer is disposed over the III-N semiconductor material, along a side of the III-N semiconductor material, and over the electron supply layer. An insulating material is arranged over the passivation layer and along opposing sidewalls of the second conductive terminal, and a gate structure is disposed over the passivation layer. The passivation layer has an uppermost surface that is directly coupled to a sidewall of the passivation layer. The insulating material extends along the sidewall of the passivation layer.

Abstract: A semiconductor device includes a compound semiconductor layer comprising a III-V material; a first layer on the compound semiconductor layer and comprising oxygen, nitrogen, and a material included in the compound semiconductor layer; a second layer over the first layer, wherein at least a portion of the second layer comprises a single crystalline structure or a polycrystalline structure; a dielectric layer over the second layer; and a source/drain electrode extending through the dielectric layer, the second layer, and the first layer and into the compound semiconductor layer.

Abstract: A control circuit driving a display panel and including a transmission interface, a charging circuit, an image driving circuit, and a loading management circuit is provided. The transmission interface is configured to be coupled to the display panel. The charging circuit is configured to charge a capacitor. The image driving circuit transforms the voltage of the capacitor into a plurality of driving signals and provides the driving signals to the display panel via the transmission interface. The loading management circuit measures the charge time of the capacitor. In response to the charge time of the capacitor exceeding a threshold value, the loading management circuit asserts a flag to indicate the occurrence of an overload.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a transistor device. The method may be performed by forming an anode and a cathode over an electron supply layer disposed on a semiconductor material. A doped III-N semiconductor material is formed over the electron supply layer, and an insulating material is formed over the electron supply layer and the doped III-N semiconductor material. The insulating material continuously extends from over the anode to over the cathode. The insulating material is patterned to form sidewalls of the insulating material that define an opening over the doped III-N semiconductor material. A gate structure is formed directly between the sidewalls of the insulating material and over the doped III-N semiconductor material.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a gate, a strained layer and a passivation layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate is disposed on the barrier layer. The strained layer is disposed on the barrier layer. The passivation layer covers the gate and the strained layer. The material of the passivation layer differs from that of the strained layer.

Abstract: A semiconductor device includes a compound semiconductor layer, an oxide layer over and contacting the compound semiconductor layer, a nitride layer over and contacting the oxide layer, and a dielectric layer over and contacting the nitride layer. At least a portion of the oxide layer comprises a first crystalline structure. At least a portion of the nitride layer comprises a second crystalline structure.

Abstract: The present disclosure, in some embodiments relates to a semiconductor device. The semiconductor device includes a layer of semiconductor material disposed over a substrate and an electron supply layer disposed over the layer of semiconductor material between an anode terminal and a cathode terminal. A layer of III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer contacts an upper surface of the electron supply layer and further contacts an upper surface and a sidewall of the layer of III-N semiconductor material. A gate structure is separated from the layer of III-N semiconductor material by the passivation layer.