Abstract: A computer-implemented method for training a natural language translation model. The computer-implemented method includes: processing one or more sets of electronic parallel documents to obtain a plurality of aligned parallel sentences; creating a first training set including a subset of the plurality of aligned parallel sentences; and training the natural language translation model in a first stage using the first training set. The computer-implemented method further includes: modifying the first training set based on translation errors detected after the first stage of training; creating a second training set based on the modified first training set and at least some of the plurality of aligned parallel sentences not in the first training set; and training the natural language translation model in a second stage using the second training set so as to improve translation performance of the natural language translation model.

Abstract: A semiconductor apparatus includes a channel layer, a barrier layer, a source contact and a drain contact, a first doped group III-V semiconductor, a group III-V semiconductor, and a second doped group III-V semiconductor. The barrier layer is disposed on the channel layer. The source contact and the drain contact are disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the first doped group III-V semiconductor and between the source contact and the drain contact. The second doped group III-V semiconductor is disposed on the group III-V semiconductor and between the source contact and the drain contact. The group III-V semiconductor has a central region covered by the second doped group III-V semiconductor and a peripheral region free from coverage by the second doped group III-V semiconductor.

Abstract: A control circuit and method for detecting a glitch signal on a bus are provided. The control circuit includes: input ends, respectively receiving a data signal and a clock signal from the bus; a counter, for calculating a time or a number of times in a low level period of the clock signal; a comparator, receiving an output of the time counted by the counter and a threshold value, and generating a comparison result by comparing the time and the threshold value; and an error detector, coupled to the comparator to receive the comparison result, and generating an error flag. When the comparison result indicates that there is a level change during the low level period of the clock signal, the error detector generates an error flag.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device includes an electron supply layer that is disposed over an upper surface of a semiconductor material and that is laterally arranged between a first conductive terminal and a second conductive terminal. A III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer is disposed over the III-N semiconductor material, along a side of the III-N semiconductor material, and over the electron supply layer. An insulating material is arranged over the passivation layer and along opposing sidewalls of the second conductive terminal, and a gate structure is disposed over the passivation layer. The passivation layer has an uppermost surface that is directly coupled to a sidewall of the passivation layer. The insulating material extends along the sidewall of the passivation layer.

Abstract: A control circuit driving a display panel and including a transmission interface, a charging circuit, an image driving circuit, and a loading management circuit is provided. The transmission interface is configured to be coupled to the display panel. The charging circuit is configured to charge a capacitor. The image driving circuit transforms the voltage of the capacitor into a plurality of driving signals and provides the driving signals to the display panel via the transmission interface. The loading management circuit measures the charge time of the capacitor. In response to the charge time of the capacitor exceeding a threshold value, the loading management circuit asserts a flag to indicate the occurrence of an overload.

Abstract: An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.

Abstract: A device may determine traffic information of a user equipment (UE) operating in a first operating mode. The first operating mode may be associated with the UE monitoring a physical downlink control channel (PDCCH), via a first bandwidth part (BWP), according to a first rate. The device may determine, based on the traffic information, that the UE is to operate in a different operating mode including one of: a second operating mode associated with monitoring the PDCCH, via the first BWP, according to a second rate exceeding the first rate, a third operating mode associated with monitoring the PDCCH, via a second BWP less than the first BWP, according to the second rate, or a fourth operating mode associated with monitoring the PDCCH, via the second BWP, according to the first rate. The device may cause the UE to transition to the different operating mode.

Abstract: In some implementations, a device may determine a signal to interference and noise ratio (SINR) value associated with a communication channel between a user equipment and the device. The device may select, based on the SINR value, a channel quality indicator (CQI) value associated with the communication channel or a sounding reference signal (SRS) from the UE to determine a multiple-input and multiple-output (MIMO) configuration for transmitting data to the UE. The device may determine the MIMO configuration according to the CQI value based on the SINR value being a first value. The device may determine the MIMO configuration according to the SRS based on the SINR value being a second value that is different than the first value. The device may transmit the data to the UE using the MIMO configuration.

Abstract: A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.

Abstract: New Radio (NR)-aware LTE scheduling is provided. An access station for a radio access network includes a first scheduling function. The first scheduling function identifies a User Equipment (UE) device that has a first active wireless connection and a second active wireless connection to the radio access network. The first scheduling function determines that expanded coverage is need for an uplink transmission for the second active wireless connection and obtains uplink scheduling information for the second active wireless connection. The first scheduling function adjusts uplink scheduling for the first active wireless connection such that power sharing is prioritized for uplink time intervals of the second active wireless connection over overlapping uplink time intervals of the first active wireless connection.

Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer is disposed on the substrate. The buffer layer includes a III-V compound which includes a first element. The buffer layer is disposed on the nucleation layer. The buffer layer has a variable concentration of the first element that incrementally increases and then decrementally decreases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: Embodiments are directed to a method of optimizing thickness of a target material film deposited on a semiconductor substrate in a semiconductor processing chamber, wherein the semiconductor processing chamber includes a magnetic assembly positioned on the semiconductor processing chamber, the magnetic assembly including a plurality of magnetic columns within the magnetic assembly. The method includes operating the semiconductor processing chamber to deposit a film of target material on a semiconductor substrate positioned within the semiconductor processing chamber, measuring an uniformity of the deposited film, adjusting a position of one or more magnetic columns in the magnetic assembly, and operating the semiconductor processing chamber to deposit the film of the target material after adjusting position of the one or more magnetic columns.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: A semiconductor device includes a compound semiconductor layer comprising a III-V material; a first layer on the compound semiconductor layer and comprising oxygen, nitrogen, and a material included in the compound semiconductor layer; a second layer over the first layer, wherein at least a portion of the second layer comprises a single crystalline structure or a polycrystalline structure; a dielectric layer over the second layer; and a source/drain electrode extending through the dielectric layer, the second layer, and the first layer and into the compound semiconductor layer.

Abstract: The present disclosure relates to a high electron mobility transistor (HEMT) and a fabrication method thereof. The HEMT may include a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a semiconductor gate disposed on the barrier layer; a metal gate disposed on the semiconductor gate, the metal gate having a trapezoidal cross-sectional shape; and a passivation layer directly contacting the metal gate. A first surface of the metal gate contacts a first surface of the semiconductor gate, and an edge of the first surface of the metal gate is located inside an edge of the first surface of the semiconductor gate.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure and a conductive layer. The substrate has a first surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The conductive layer is disposed on the second nitride semiconductor layer. The conductive layer has a first length extending in a first direction substantially parallel to the first surface of the substrate, a second length extending in a second direction substantially perpendicular to the first direction—from a cross section view perspective—wherein the second length is greater than the first length.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

Abstract: An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.

Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from wide to narrow with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.