Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer on the substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a first area and a second area, and the second nitride semiconductor layer has single crystals. The semiconductor device includes an electrode in contact with the first area. A first concentration of Aluminum (Al) of the first area is less than a second concentration of Al of the second area, and the single crystals in the first area take over a crystal structure of the first nitride semiconductor layer.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

Abstract: A system for simulating a wireless communication network over a wired network may comprise a plurality of physical UEs, one or more RANs, and a channel condition emulator. The plurality of UEs may be coupled to one another through the wired network. The one or more RANs may be simulated in software to simulate data transmissions between the plurality of UEs. The channel condition emulator may be simulated in software to derive channel conditions for each of the plurality of UEs based on their current location. The channel condition emulator may further provide the channel conditions to the plurality of UEs and the one or more RANs.

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body cofntact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

Abstract: A high voltage device is used as a lower switch in a power stage of a switching regulator. The high voltage device includes at least one lateral diffused metal oxide semiconductor (LDMOS) device, a first isolation region, a second isolation region, a third isolation region, and a current limiting device. The first isolation region is located in a semiconductor layer, and encloses the LDMOS device. The second isolation region has a first conductivity type, and encloses the first isolation region in the semiconductor layer. The third isolation region has a second conductivity type, and encloses the second isolation region in the semiconductor layer. The current limiting device is electrically connected to the second isolation region, and is configured to operably suppress a parasitic silicon controlled rectifier (SCR) from being turned on.

Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer is disposed on the substrate. The buffer layer includes a III-V compound which includes a first element. The buffer layer is disposed on the nucleation layer. The buffer layer has a variable concentration of the first element that decrementally decreases and then incrementally increases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer includes a compound which includes a first group III element and is devoid of a second group III element. The buffer layer includes a III-V compound which includes the first and second group III elements. The buffer layer has an element ratio of the first group III element to the second group III element that decrementally decreases and then incrementally increases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer includes a compound which includes a first group III element and is devoid of a second group III element. The buffer layer includes a III-V compound which includes the first and second group III elements. The buffer layer has an element ratio of the first group III element to the second group III element that incrementally increases and then decrementally decreases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. An oscillation rate in the concentration of the first element per unit thickness of the buffer layer varies with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

Abstract: A semiconductor device includes a nucleation layer, a first buffer layer, a first nitride-based semiconductor layer, and a second buffer layer. The nucleation layer includes a compound which includes a first element. The first buffer layer includes a III-V compound which includes the first element. A concentration of the first element varies with respect to a first reference point within the first buffer layer. The first nitride-based semiconductor layer is disposed on the first buffer layer. The second buffer layer includes a III-V compound which includes a second element different than the first element. The second buffer layer is disposed on and forms an interface with the first nitride-based semiconductor layer. A concentration of the second element varies to cyclically oscillate as a function of a distance within a thickness of the second buffer layer, which occurs with respect to a second reference point within the second buffer layer.

Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer is disposed on the substrate. The buffer layer includes a III-V compound which includes a first element. The buffer layer is disposed on the nucleation layer. The buffer layer has a variable concentration of the first element that decrementally decreases and then incrementally increases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. A first oscillation rate between a first reference point and a second reference point within the buffer layer is greater than a second oscillation rate between the second reference point and a third reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer includes a compound which includes a first group III element and is devoid of a second group III element. The buffer layer includes a III-V compound which includes the first and second group III elements. The buffer layer has a variable concentration of the second group III element that incrementally increases and then decrementally decreases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from narrow to wide with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. A first oscillation rate between a first reference point and a second reference point within the buffer layer is less than a second oscillation rate between the second reference point and a third reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer includes a compound which includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element cyclically oscillating with respect to first and second reference points within a buffer layer. The first and second reference points are respectively positioned at first and second distances from a top surface of the nucleation layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: A semiconductor apparatus includes a channel layer, a barrier layer, a source contact and a drain contact, a first doped group III-V semiconductor, a group III-V semiconductor, and a second doped group III-V semiconductor. The barrier layer is disposed on the channel layer. The source contact and the drain contact are disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the first doped group III-V semiconductor and between the source contact and the drain contact. The second doped group III-V semiconductor is disposed on the group III-V semiconductor and between the source contact and the drain contact. The group III-V semiconductor has a central region covered by the second doped group III-V semiconductor and a peripheral region free from coverage by the second doped group III-V semiconductor.

Abstract: A system for simulating a wireless communication network over a wired network may comprise a plurality of physical UEs, one or more RANs, and a channel condition emulator. The plurality of UEs may be coupled to one another through the wired network. The one or more RANs may be simulated in software to simulate data transmissions between the plurality of UEs. The channel condition emulator may be simulated in software to derive channel conditions for each of the plurality of UEs based on their current location. The channel condition emulator may further provide the channel conditions to the plurality of UEs and the one or more RANs.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.