Patents by Inventor Chin-Fu Lin

Chin-Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130078778
    Abstract: A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Publication number: 20130056827
    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Inventors: Shih-Hung Tsai, Chien-Ting Lin, Chin-Cheng Chien, Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chun-Yuan Wu
  • Patent number: 8390087
    Abstract: The present invention discloses an image sensor package structure with a large air cavity. The image sensor package structure includes a substrate, a chip, a cover and a package material. The chip is combined with the substrate. A plastic sheet of the cover is adhered to the chip and a transparent lid of the cover is combined with the plastic sheet to provide a covering over a sensitization area of the chip so as to form an air cavity. The package material is arranged on the substrate and encapsulated around the chip and the cover. The plastic sheet having a predetermined thickness can increase the distance between the transparent lid and the chip to enlarge the air cavity. Thus, the image-sensing effect of the image sensor package structure can be improved and the ghost image problem resulting from multi-refraction and multi-reflection of light can be minimized.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: March 5, 2013
    Assignee: Kingpak Technology Inc.
    Inventors: Hsiu-Wen Tu, Ren-Long Kuo, Young-Houng Shiao, Tsao-Pin Chen, Mon-Nam Ho, Chih-Cheng Hsu, Chin-Fu Lin, Chung-Hsien Hsin
  • Publication number: 20130045595
    Abstract: The method for processing a metal layer including the following steps is illustrated. First, a semiconductor substrate is provided. Then, a metal layer is formed over the semiconductor substrate. Furthermore, a microwave energy is used to selectively heat the metal layer without affecting the underlying semiconductor substrate and other formed structures, in which the microwave energy has a predetermined frequency in accordance with a material of the metal layer, and the predetermined frequency ranges between 1 KHz to 1 MHz.
    Type: Application
    Filed: August 16, 2011
    Publication date: February 21, 2013
    Inventors: Tsun-Min Cheng, Chien-Chao Huang, Chin-Fu Lin, Chi-Mao Hsu, Yen-Liang Lu, Chun-Ling Lin
  • Publication number: 20130043513
    Abstract: A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.
    Type: Application
    Filed: August 19, 2011
    Publication date: February 21, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Liang-An HUANG, Yu-Chun Huang, Chin-Fu Lin, Yu-Ciao Lin, Yu-Chieh Lin, Hsin-Liang Liu, Chun-Hung Cheng, Yuan-Cheng Yang, Yau-Kae Sheu
  • Publication number: 20130045579
    Abstract: A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 21, 2013
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Publication number: 20130037886
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Application
    Filed: August 10, 2011
    Publication date: February 14, 2013
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • Patent number: 8361854
    Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 29, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • Publication number: 20130009288
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Inventors: Shu-Hui Hu, Shih-Feng Su, Hui-Shen Shih, Chih-Chien Liu, Po-Chun Chen, Ya-Jyuan Hung, Bin-Siang Tsai, Chin-Fu Lin
  • Publication number: 20130001707
    Abstract: A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventors: Chien-Liang Lin, Ying-Wei Yen, Yu-Ren Wang, Chan-Lon Yang, Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Publication number: 20120326243
    Abstract: A transistor having an aluminum metal gate includes a substrate, a high-k gate dielectric layer, an aluminum metal gate and a source/drain region. The high-k gate dielectric layer is disposed on the substrate. The aluminum metal gate includes a work function tuning layer and an aluminum metal layer disposed orderly on the high-k gate dielectric layer, where the aluminum metal layer comprises a first aluminum metal layer and a second aluminum metal layer. Furthermore, the source/drain region is disposed in the substrate at each of two sides of the aluminum metal gate.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 27, 2012
    Inventors: Hsin-Fu Huang, Chi-Mao Hsu, Min-Chuan Tsai, Chin-Fu Lin, Chun-Hsien Lin
  • Publication number: 20120319198
    Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Publication number: 20120322218
    Abstract: A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming LAI, Yi-Wen Chen, Zhi-Cheng Lee, Tong-Jyun Huang, Che-Hua Hsu, Kun-Hsien Lin, Tzung-Ying Lee, Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin
  • Publication number: 20120319179
    Abstract: A metal gate includes a substrate, a gate dielectric layer, a work function metal layer, an aluminum nitride layer and a stop layer. The gate dielectric layer is located on the substrate. The work function metal layer is located on the gate dielectric layer. The aluminum nitride layer is located on the work function metal layer. The stop layer is located on the aluminum nitride layer.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Inventors: Hsin-Fu Huang, Zhi-Cheng Lee, Chi-Mao Hsu, Chin-Fu Lin, Kun-Hsien Lin, Tzung-Ying Lee, Min-Chuan Tsai
  • Publication number: 20120322260
    Abstract: A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • Publication number: 20120305403
    Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 6, 2012
    Inventors: Chun-Ling Lin, Yen-Liang Lu, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Meng-Hong Tsai
  • Patent number: 8324118
    Abstract: A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M1Ox) of a first metal (M1) and the second metal oxide layer includes a metal oxide ((M1M2Oy) of the first metal and a second metal (M2).
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: December 4, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Chun-Yuan Wu, Chin-Fu Lin, Teng-Chun Tsai, Chin-Cheng Chien
  • Publication number: 20120295437
    Abstract: A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a through-silicon via in the semiconductor substrate; covering a liner in the through-silicon via; performing a baking process on the liner; forming a barrier layer on the liner; and forming a through-silicon via electrode in the through-silicon via.
    Type: Application
    Filed: May 16, 2011
    Publication date: November 22, 2012
    Inventors: Yen-Liang Lu, Chun-Ling Lin, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Meng-Hong Tsai
  • Publication number: 20120292721
    Abstract: A method of fabricating a semiconductor device includes following steps. A substrate is provided, wherein a first dielectric layer having a trench therein is formed on the substrate, a source/drain region is formed in the substrate at two sides of the trench, and a second dielectric layer is formed on the substrate in the trench. A first physical vapor deposition process is performed to form a Ti-containing metal layer in the trench. A second physical vapor deposition process is performed to form an Al layer on the Ti-containing metal layer in the trench. A thermal process is performed to anneal the Ti-containing metal layer and the Al layer so as to form a work function metal layer. A metal layer is formed to fill the trench.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 22, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Fu Huang, Kun-Hsien Lin, Chi-Mao Hsu, Min-Chuan Tsai, Tzung-Ying Lee, Chin-Fu Lin
  • Publication number: 20120282783
    Abstract: A method for fabricating high-k dielectric layer is disclosed. The method includes the steps of: providing a substrate; and forming a plurality of high-k dielectric layers by using a plurality of reacting gases to perform a plurality of process stages on the surface of the substrate, wherein at least one of the reacting gases comprises different flow rate in the fabrication stages.
    Type: Application
    Filed: May 3, 2011
    Publication date: November 8, 2012
    Inventors: Jui-Chen Chang, Chen-Kuo Chiang, Chin-Fu Lin, Chih-Chien Liu