Patents by Inventor Chin Li

Chin Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250066756
    Abstract: Provided are various embodiments relating to variant asparaginase polypeptides with enhanced stability, pharmacodynamics, and/or reduced immunogenicity. The variant asparaginase polypeptides may be used as therapeutics in mammals, including human, canines, felines, and equines.
    Type: Application
    Filed: August 23, 2024
    Publication date: February 27, 2025
    Applicant: Kindred Biosciences, Inc.
    Inventors: Hangjun Zhan, Lam Nguyen, Richard Chin, Shyr Jiann Li
  • Publication number: 20250058510
    Abstract: A composite material and a method for manufacturing the composite material are provided. The composite material includes a laminated structure formed by co-extruding a thermoplastic elastomer and a modified thermoplastic elastomer. The use of the thermoplastic elastomer and the modified thermoplastic elastomer in the composite material can significantly reduce emissions during the manufacturing process, and the manufacturing process is simple and stable, and can improve the wear resistance of the composite material.
    Type: Application
    Filed: July 23, 2024
    Publication date: February 20, 2025
    Inventors: CHIH-YI LIN, KUO-KUANG CHENG, CHI-CHIN CHIANG, KUN LIN CHIANG, DE-YU LI
  • Patent number: 12224248
    Abstract: A semiconductor wafer includes semiconductor dies and laser grooves formed in the scribe lines along the long edges of the semiconductor dies. A laser groove extends between the long edges of two adjacent semiconductor dies to encompass the corners of the two adjacent semiconductor dies. When diced, the resulting semiconductor dies have portions of the corners removed.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: February 11, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Chin-Tien Chiu, Jia Li, Dongpeng Xue, Huirong Zhang, Guocheng Zhong, Xiaohui Wang, Hua Tan
  • Patent number: 12224285
    Abstract: An integrated circuit includes a set of active regions, a first contact, a set of gates, a first and second conductive line and a first and second via. The set of active regions extends in a first direction, and is on a first level. The first contact extends in a second direction, is on a second level, and overlaps at least a first active region. The set of gates extends in the second direction, overlaps the set of active regions, and is on a third level. The first conductive line and the second conductive line extend in the first direction, overlap the first contact, and are on a fourth level. The first via electrically couples the first contact and the first conductive line together. The second via electrically couples the first contact and the second conductive line together.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Wei Hsu, Shun Li Chen, Ting Yu Chen, Hui-Zhong Zhuang, Chih-Liang Chen
  • Publication number: 20250038078
    Abstract: A bonding structure and a package structure are provided. The bonding structure includes a first pad and a plurality of first wires. The first pad has a top surface including a first region and a second region, wherein the second region is closer to an edge of the top surface of the first pad than the first region is. The first wires are on the top surface of the first pad, wherein a number of the first wires on the first region is greater than a number of the first wires on the second region.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 30, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Chin-Li KAO
  • Patent number: 12202574
    Abstract: Disclosed herein is a buoyant structure for offshore deployment. The buoyant structure comprises a first deck having a first channel through the first deck; a second deck having a second channel through the second deck, wherein the first deck and second deck are coupled to each other and arranged spaced apart from each other; and a plurality of floatable substructures coupled to and around at least one of the first deck and the second deck, the plurality of floatable substructures arranged spaced apart from one another, wherein the first channel and the second channel are aligned to receive at least a portion of a tower of a wind turbine.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: January 21, 2025
    Assignee: SEATRIUM (SG) PTE. LTD.
    Inventors: Shuo Wang, Maya Sreedharan, Chin Lee Lim, Sinik Jang, Xiao Li Chia
  • Publication number: 20240413115
    Abstract: A package structure is provided. The package structure includes an electronic component, an encapsulant, a first conductive pillar, a first dielectric layer. The electronic component has an active surface. The encapsulant encapsulates the electronic component and exposes the active surface of the electronic component. The first conductive pillar is over the active surface of the electronic component, wherein an upper surface of the first conductive pillar includes a concave portion. The first dielectric layer is over the encapsulant and the active surface of the electronic component, wherein the first dielectric layer defines an opening exposing the concave portion of the first conductive pillar.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Ling YEH, Yuan-Feng CHIANG, Chung-Hung LAI, Chin-Li KAO
  • Publication number: 20240339383
    Abstract: An electronic device and a method of manufacturing an electronic device are provided. The electronic device includes an electronic component, a carrier, and a lead. The electronic component has a lateral surface. The carrier supports the electronic component. The lead is electrically connected to the electronic component and disposed adjacent to the lateral surface of the electronic component. The carrier and the lead are configured to block an electromagnetic wave between the electronic component and an external of the electronic device.
    Type: Application
    Filed: April 7, 2023
    Publication date: October 10, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ko-Pu WU, Chih-Hung HSU, Chin Li HUANG, Chieh-Yin LIN, Yuan-Chun CHEN, Kai-Sheng PAI
  • Patent number: 12113044
    Abstract: A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a package component having a first mounting surface and a second mounting surface; and a first electronic component having a first conductive pad signal communicatively mounted on the first mounting surface through a first type connector; wherein the first type connector comprises a first solder composition having a lower melting point layer sandwiched between a pair of higher melting point layers, wherein the lower melting point layer is composed of alloys capable of forming a room temperature eutectic.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: October 8, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shan-Bo Wang, Chin-Li Kao, An-Hsuan Hsu
  • Publication number: 20240334586
    Abstract: A package structure is provided. The package structure includes an electronic component, a heat dissipating element, a thermal interfacing unit, and a confining structure. The electronic component has an upper surface. The heat dissipating element is over the upper surface of the electronic component. The thermal interfacing unit is between the upper surface of the electronic component and the heat dissipating element. The thermal interfacing unit includes a thermal interfacing material (TIM). The TIM is attached to the confining structure by capillary force.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Hung-Hsien HUANG, Chin-Li KAO
  • Publication number: 20240304450
    Abstract: An electronic package structure includes a first electronic component, a first thermal conductive structure and a second thermal conductive structure. The first thermal conductive structure is disposed over the first electronic component. The second thermal conductive structure is disposed between the first electronic component and the first thermal conductive structure. A first heat transfer rate of the second thermal conductive structure along a first direction from the first electronic component to the first thermal conductive structure is greater than a second heat transfer rate of the second thermal conductive structure along a second direction nonparallel with the first direction from the first electronic component to an element other than the first thermal conductive structure.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 12, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Chin-Li KAO
  • Publication number: 20240121133
    Abstract: Systems and methods for an Internet of Things (IoT), smart home climate control and communication system are provided. The IoT, smart home climate control and communication system includes a first smart home device that receives signal sources from a wide area network, transmits signals, data and commands to one or more smart home devices in a home or building in an IoT LAN. The first smart home device also receives signals, data and commands from the one or more smart home devices in the home or building on the IoT LAN, and transmits signals, data and/or commands to the wide area network. The IoT LAN is distinct from a residential wireless LAN.
    Type: Application
    Filed: April 11, 2023
    Publication date: April 11, 2024
    Inventor: Max Chin Li
  • Publication number: 20240096628
    Abstract: A photo mask includes a plurality of device features, a first assist feature, and a second assist feature. The device features are in a patterning region of a device region. The first assist feature are in the patterning region and adjacent to the device features. The first assist feature is for correcting an optical proximity effect in a photolithography process. The second assist feature is in a non-patterning region of the device region. The second assist feature is a sub-resolution correction feature, and a first distance between the second assist feature and one of the device features closest to the second assist feature is greater than a second distance between adjacent two of the device features.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bao-Chin LI, Chung-Kai HUANG, Ko-Pin KAO, Ching-Yen HSAIO
  • Publication number: 20240063159
    Abstract: A package structure is disclosed. The package structure includes a substrate including a conductive element and a plurality of wires having a surface area through which heat of the conductive element can be dissipated, lowering a bonding temperature of the conductive element. The package structure also includes a conductive layer disposed between the conductive element of the substrate and the plurality of wires. The conductive contact layer attaches the plurality of wires over the conductive element.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Chin-Li KAO
  • Publication number: 20240035971
    Abstract: A fluorescence lifetime imaging microscopy system comprises a microscope comprising an excitation source configured to direct an excitation energy to an imaging target, and a detector configured to measure emissions of energy from the imaging target, and a non-transitory computer-readable medium with instructions stored thereon, which perform steps comprising collecting a quantity of measured emissions of energy from the imaging target as measured data, providing a trained neural network configured to calculate fluorescent decay parameters from the quantity of measured emissions of energy, providing the data to the trained neural network, and calculating at least one fluorescence lifetime parameter with the neural network from the measured data, wherein the measured data comprises an input fluorescence decay histogram, and wherein the neural network was trained by a generative adversarial network. A method of training a neural network and a method of acquiring an image are also described.
    Type: Application
    Filed: September 17, 2021
    Publication date: February 1, 2024
    Inventors: Hsin-Chih Yeh, Yuan-I Chen, Yin-Jui Chang, Shih-Chu Liao, Trung Duc Nguyen, Soonwoo Hong, Yu-An Kuo, Hsin-Chin Li
  • Patent number: 11855034
    Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: December 26, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung-Hung Lai, Chin-Li Kao, Chih-Yi Huang, Teck-Chong Lee
  • Patent number: 11854808
    Abstract: A photo mask includes a plurality of device features, a first assist feature, and a second assist feature. The device features are in a patterning region of a device region. The first assist feature are in the patterning region and adjacent to the device features. The first assist feature is for correcting an optical proximity effect in a photolithography process. The second assist feature is in a non-patterning region of the device region. The second assist feature is a sub-resolution correction feature, and a first distance between the second assist feature and one of the device features closest to the second assist feature is greater than a second distance between adjacent two of the device features.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bao-Chin Li, Chung-Kai Huang, Ko-Pin Kao, Ching-Yen Hsaio
  • Publication number: 20230408787
    Abstract: An imaging lens assembly includes a first plastic lens element and a second plastic lens element arranged along an optical axis. The first plastic lens element includes, in order from a paraxial region to a peripheral region, a first optically effective portion, a first size reduction portion and a first peripheral portion. An object-side surface and an image-side surface of the first size reduction portion each has a roughened surface. The first peripheral portion is to be in physical contact and assembled with adjacent components. The second plastic lens element includes, in order from a paraxial region to a peripheral region, a second optically effective portion, a second size reduction portion and a second peripheral portion. An object-side surface and an image-side surface of the second size reduction portion each has a roughened surface. The second peripheral portion is to be in physical contact and assembled with adjacent components.
    Type: Application
    Filed: August 12, 2022
    Publication date: December 21, 2023
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Lin An CHANG, Chin Li HSIEH, Chun-Hua TSAI
  • Publication number: 20230268314
    Abstract: A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a package component having a first mounting surface and a second mounting surface; and a first electronic component having a first conductive pad signal communicatively mounted on the first mounting surface through a first type connector; wherein the first type connector comprises a first solder composition having a lower melting point layer sandwiched between a pair of higher melting point layers, wherein the lower melting point layer is composed of alloys capable of forming a room temperature eutectic.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shan-Bo WANG, Chin-Li KAO, An-Hsuan HSU
  • Patent number: D1061105
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: February 11, 2025
    Assignees: BABY TREND, INC., Dong Guan Golden Prosper Baby Products Co., Ltd.
    Inventors: Mark Asai, Michael Cavins, Chin-Kuan Lac, Jie Hu, Shaoqin Li