Abstract: A ceiling fan includes a body having a disk which is driven by a motor. Multiple frames are connected to the disk and each frame has a rod which is connected between at least two seats and the disk. The at least two seats each are positioned by an inclination angle relative to a horizontal plane. A height difference is formed between the at least two seats of each rod. A blade is connected to each of the at least two seats of each rod of each frame. The ceiling fan includes less number of seats while more blades are connected to the seats.

Abstract: The measurement equipment includes a rack, a first image capturing device, a second image capturing device, a third image capturing device and a fourth image capturing device. Wherein, the first image capturing device and the second image capturing device capture an entire image of a to-be-measured object, the third image capturing device and the fourth image capturing device capture a plurality of local images of a plurality of local areas of the to-be-measured object, and the entire image and the local images and are simultaneously captured.

Abstract: An optimization method of image depth information and an image processing apparatus are provided. A to-be-repaired depth map generated based on a left image and a right image is obtained. A superpixel segmenting process is performed on the left image or the right image to obtain multiple superpixels. A plurality of image segments are obtained by aggregating the superpixels according to pixel information in the superpixels. A hole filling process is performed on holes of the to-be-repaired depth map to obtain a hole-filled depth map. A statistical analysis is performed on first valid depth values of the to-be-repaired depth map and second valid depth values of the hole-filled depth map to obtain a plurality of optimized depth values by using the ranges of the image segments, the ranges of the superpixels, the to-be-repaired depth map, and the hole-filled depth map.

Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.

Abstract: The measurement equipment includes a rack, a first image capturing device, a second image capturing device, a third image capturing device and a fourth image capturing device. Wherein, the first image capturing device and the second image capturing device capture an entire image of a to-be-measured object, the third image capturing device and the fourth image capturing device capture a plurality of local images of a plurality of local areas of the to-be-measured object, and the entire image and the local images and are simultaneously captured.

Abstract: Materials and methods for preparing reactive lignin and for preparing a bio-based adhesive are described herein.

Abstract: A semiconductor device includes a first die, a second die, an encapsulant, a first dielectric layer, and at least one first trace. The first die includes a first surface and a second surface opposite to the first surface and includes at least one first pad disposed adjacent to the first surface of the first die. The second die includes a first surface and a second surface opposite to the first surface and includes at least one second pad disposed adjacent to the first surface of the second die. The first dielectric layer is disposed on at least a portion of the first surface of the first die and at least a portion of the first surface of the second die. The first trace is disposed on the first dielectric layer, which connects the first pad to the second pad, and the first trace comprises an end portion disposed adjacent to the first pad and a body portion, and the end portion extends at an angle ?1 relative to a direction of extension of the body portion.

Abstract: A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.

Abstract: Cerium oxide nanorods having a variety of aspect ratios can be produced by providing a first mixture that includes a cerium precursor material, and using microwave to heat the first mixture to a first temperature for a period of time to produce first plurality of cerium oxide nanorods having a first range of aspect ratios. A second mixture that includes a cerium precursor material heated using microwave to a second temperature for a period of time to produce second plurality of cerium oxide nanorods having a second range of aspect ratios. The first plurality of cerium oxide nanorods and the second plurality of cerium oxide nanorods are mixed to produce third plurality of cerium oxide nanorods having the third range of aspect ratios that is broader than the first range or the second range.

Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.

Abstract: Disclosed herein is a bacteriochlorin-based organic dye represented by Formula (II): wherein the substituents contained in Formula (II) are as defined herein. The bacteriochlorin-based organic dye is stable in air, and may be used as a photosensitizer in dye-sensitized solar cell.

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

Abstract: The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.

Abstract: A catalyst that includes cerium oxide having a fluorite lattice structure is provided. The cerium oxide includes cerium atoms in mixed valence states of Ce3+/Ce4+, in which the ratio of Ce3+/(Ce3++Ce4+) in the lattice ranges from 40% to 90% at 20° C. The valence states Ce3+ and Ce4+ are reversible in reduction and oxidation reactions, and the cerium oxide maintains catalytic ability at temperatures at least up to 450° C.

Abstract: The present invention provides a novel stacked inductor and an electronic component module having the novel stacked inductor, wherein the multilayer stacked inductor is fabricated by stacking a top magnetic material layer, a plurality of first middle magnetic material layers, at least one second middle magnetic material layer, at least one non-magnetic material layer, and a bottom magnetic material layer. In the present invention, a second metal layer formed on the non-magnetic material layer and a first metal layer formed on the first middle magnetic material layer have a first line width ratio, and a third metal layer formed on the second middle magnetic material layer and the first metal layer have a second line width ratio. Therefore, the DC resistance and the quality factor of this novel multilayer stacked inductor can be optimized based on the first and second line width ratio.

Abstract: Embodiments disclosed herein provide coated particles that can be used, for example, in the extraction of oil and gas from subterranean formations.

Abstract: Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes thereof. An interposer substrate defines a cavity and further includes a reinforcement structure, wherein the reinforcement structure is used to control warpage of the semiconductor package structure.