Patents by Inventor Chin Li

Chin Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384381
    Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chung-Hung LAI, Chin-Li KAO, Chih-Yi HUANG, Teck-Chong LEE
  • Patent number: 11496694
    Abstract: A dual sensor imaging system and an imaging method thereof are provided. The dual sensor imaging system includes at least one color sensor, at least one infrared ray (IR) sensor, a storage device, and a processor. The processor is configured to load and execute a computer program stored in the storage device to: identify an imaging scene of the dual sensor imaging system; control the color sensor and the IR sensor to respectively capture multiple color images and multiple IR images by adopting multiple exposure conditions suitable for the imaging scene; adaptively select a combination of the color image and the IR image that can reveal details of the imaging scene; and fuse the selected color image and IR image to generate a scene image with details of the imaging scene.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: November 8, 2022
    Assignee: Altek Semiconductor Corp.
    Inventors: Shih-Yuan Peng, Shu-Chun Cheng, Hsu-Lien Huang, Yun-Chin Li, Kuo-Ming Lai
  • Patent number: 11496660
    Abstract: A dual sensor imaging system and a depth map calculation method thereof are provided. The dual sensor imaging system includes at least one color sensor, at least one infrared ray (IR) sensor, a storage device, and a processor. The processor is configured to load and execute a computer program stored in the storage device to: control the color sensor and the IR sensor to respectively capture multiple color images and multiple IR images by adopting multiple exposure conditions suitable for an imaging scene, adaptively select a combination of the color image and the IR image that are comparable to each other from the color images and the IR images; and calculate a depth map of the imaging scene by using the selected color image and IR image.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: November 8, 2022
    Assignee: Altek Semiconductor Corp.
    Inventors: Shih-Yuan Peng, Shu-Chun Cheng, Hsu-Lien Huang, Yun-Chin Li, Kuo-Ming Lai
  • Patent number: 11450596
    Abstract: A lead frame includes a die paddle, a plurality of leads, at least one connector and a bonding layer. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle and an outer lead portion opposite to the inner lead portion. The connector is connected to the die paddle and the inner lead portions of the leads. The bonding layer is disposed on a lower surface of the die paddle and a lower surface of each of the outer lead portions.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: September 20, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi-Cheng Hsu, Chih-Hung Hsu, Mei-Lin Hsieh, Yuan-Chun Chen, Yu-Shun Hsieh, Ko-Pu Wu, Chin Li Huang
  • Patent number: 11430761
    Abstract: Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: August 30, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yun-Ching Hung, Yung-Sheng Lin, Chin-Li Kao
  • Patent number: 11418719
    Abstract: A dual sensor imaging system and a calibration method thereof are provided. The dual sensor imaging system includes at least one color sensor, at least one infrared ray (IR) sensor, a storage device, and a processor. The processor is configured to load and execute a computer program stored in the storage device to: control the color sensor and the IR sensor to respectively capture multiple color images and multiple IR images of an imaging scene by adopting multiple capturing conditions; calculate multiple color image parameters of the color image captured under each capturing condition and multiple IR image parameters of the IR image captured under each capturing condition to be used to calculate a difference between a brightness of the color image and a brightness of the IR image; and determine an exposure setting suitable for the color sensor and the IR sensor according to the calculated difference.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: August 16, 2022
    Assignee: Altek Semiconductor Corp.
    Inventors: Shih-Yuan Peng, Shu-Chun Cheng, Hsu-Lien Huang, Yun-Chin Li, Kuo-Ming Lai
  • Publication number: 20220230946
    Abstract: A substrate structure and a semiconductor package structure are provided. The substrate structure includes a first dielectric layer, a pad and a conductive structure. The first dielectric layer has a first surface and a second surface opposite to the first surface. The pad is adjacent to the first surface and at least partially embedded in the first dielectric layer. The first dielectric layer has an opening exposing the pad, and a width of the opening is less than a width of the pad. The conductive structure is disposed on the pad and composed of a first portion outside the opening of the first dielectric layer and a second portion embedded in the opening of the first dielectric layer. The first portion has an aspect ratio exceeding 1.375.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Wei SHIH, Sheng-Wen YANG, Chung-Hung LAI, Chin-Li KAO
  • Patent number: 11309253
    Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a first conductive structure and a second conductive structure. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure is bonded to the first conductive structure. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. A distribution density of the circuit layer of the first conductive structure is greater than a distribution density of the circuit layer of the second conductive structure. A size of the second conductive structure is less than a size of the first conductive structure.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: April 19, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chin-Li Kao
  • Patent number: 11257776
    Abstract: A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Sheng Lin, Chin-Li Kao, Hsu-Nan Fang
  • Patent number: 11244909
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The first electronic device is disposed on the wiring structure. The second electronic device is disposed on the wiring structure. The first electronic device and the second electronic device are disposed side by side. A gap between the first electronic device and the second electronic device is greater than or equal to about 150 ?m.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: February 8, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Fan-Yu Min, Chen-Hung Lee, Wei-Hang Tai, Yuan-Tzuo Luo, Wen-Yuan Chuang, Chun-Cheng Kuo, Chin-Li Kao
  • Publication number: 20210409240
    Abstract: Systems and methods for an Internet of Things (IoT), smart home climate control and communication system are provided. The IoT, smart home climate control and communication system includes a first smart home device that receives signal sources from a wide area network, transmits signals, data and commands to one or more smart home devices in a home or building in an IoT LAN. The first smart home device also receives signals, data and commands from the one or more smart home devices in the home or building on the IoT LAN, and transmits signals, data and/or commands to the wide area network. The IoT LAN is distinct from a residential wireless LAN.
    Type: Application
    Filed: July 6, 2021
    Publication date: December 30, 2021
    Inventor: Max Chin Li
  • Publication number: 20210335715
    Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a first conductive structure and a second conductive structure. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure is bonded to the first conductive structure. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. A distribution density of the circuit layer of the first conductive structure is greater than a distribution density of the circuit layer of the second conductive structure. A size of the second conductive structure is less than a size of the first conductive structure.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chin-Li KAO
  • Patent number: 11155568
    Abstract: Materials and methods for preparing reactive lignin and for preparing a bio-based adhesive are described herein.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 26, 2021
    Assignee: NUtech Ventures
    Inventors: Mark Alan Helle, Chin Li Cheung
  • Patent number: 11127650
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 21, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien Lin Chang Chien, Chiu-Wen Lee, Hung-Jung Tu, Chang Chi Lee, Chin-Li Kao
  • Publication number: 20210287999
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The first electronic device is disposed on the wiring structure. The second electronic device is disposed on the wiring structure. The first electronic device and the second electronic device are disposed side by side. A gap between the first electronic device and the second electronic device is greater than or equal to about 150 ?m.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 16, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Fan-Yu MIN, Chen-Hung LEE, Wei-Hang TAI, Yuan-Tzuo LUO, Wen-Yuan CHUANG, Chun-Cheng KUO, Chin-Li KAO
  • Publication number: 20210272866
    Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ya-Yu HSIEH, Chin-Li KAO, Chung-Hsuan TSAI, Chia-Pin CHEN
  • Publication number: 20210265231
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 26, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien Lin CHANG CHIEN, Chiu-Wen LEE, Hung-Jung TU, Chang Chi LEE, Chin-Li KAO
  • Publication number: 20210257331
    Abstract: Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 19, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yun-Ching HUNG, Yung-Sheng LIN, Chin-Li KAO
  • Publication number: 20210243344
    Abstract: A dual sensor imaging system and a depth map calculation method thereof are provided. The dual sensor imaging system includes at least one color sensor, at least one infrared ray (IR) sensor, a storage device, and a processor. The processor is configured to load and execute a computer program stored in the storage device to: control the color sensor and the IR sensor to respectively capture multiple color images and multiple IR images by adopting multiple exposure conditions suitable for an imaging scene, adaptively select a combination of the color image and the IR image that are comparable to each other from the color images and the IR images; and calculate a depth map of the imaging scene by using the selected color image and IR image.
    Type: Application
    Filed: March 29, 2021
    Publication date: August 5, 2021
    Applicant: Altek Semiconductor Corp.
    Inventors: Shih-Yuan Peng, Shu-Chun Cheng, Hsu-Lien Huang, Yun-Chin Li, Kuo-Ming Lai
  • Publication number: 20210218871
    Abstract: A dual sensor imaging system and a privacy protection imaging method thereof are provided. The system is configured to control at least one color sensor and at least one IR sensor to respectively capture multiple color images and multiple IR images by adopting multiple exposure conditions adapted for an imaging scene, adaptively select a combination of the color image and the IR image that can reveal details of the imaging scene, detect a feature area with features of a target of interest in the color image, and fuse the color image and the IR image to generate a fusion image with the details of the imaging scene, and crop an image of the feature area of the fusion image to be replaced with an image not belonging to the IR image, so as to generate a scene image.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 15, 2021
    Applicant: Altek Semiconductor Corp.
    Inventors: Shih-Yuan Peng, Shu-Chun Cheng, Hsu-Lien Huang, Yun-Chin Li, Kuo-Ming Lai