Abstract: The present invention provides a compound of Formula (I): or an enantiomer, an enantiomeric mixture, or a pharmaceutically acceptable salt thereof; wherein the variables are as defined herein. The present invention further provides pharmaceutical compositions comprising such compounds; and methods of using such compounds for treating a disease or condition mediated by mixed lineage leukemia 1 (MLL1).

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A method of manufacturing a semiconductor device includes at least the following steps. An opening is formed in a substrate. A first protection layer is formed on an exposed surface of the opening. A first etching process is performed on the opening with the first protection layer thereon, to simultaneously remove the first protection layer on a sidewall of the opening and a portion of the substrate to deepen a depth of the opening.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a semiconductor layer disposed on the substrate, a source/drain region disposed adjacent to the semiconductor layer, a gate structure disposed on the semiconductor layer, an interfacial spacer layer having a triangular cross-sectional profile disposed along sidewall of the gate structure, and a gate spacer. The gate spacer includes a first spacer portion having a first bottom surface with a substantially linear profile disposed on the semiconductor layer and a second spacer portion having a second bottom surface with a sloped profile disposed on the interfacial spacer layer.

Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.

Abstract: A DC-DC converter for converting an input voltage from a battery source includes a piezoelectric converter and a switched capacitor network between the battery source and the piezoelectric converter. The switched capacitor network provides a flying capacitor configured to be soft-charged and soft discharged due to an inductive operation of the piezoelectric converter such that charge-sharing loss of the flying capacitor is eliminated.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.

Abstract: A method of the present disclosure includes forming a fin-shaped structure including a plurality of semiconductor layers, a first hard mask layer, a second hard mask layer, and a third hard mask layer, forming a patterned masking layer having a mask portion and a window portion, wherein the third hard mask layer is exposed through the window portion, performing a first etch process to expose the second hard mask layer through the window portion, performing a second etch process to etch the exposed second hard mask layer and to leave behind second hard mask layer residues, performing a third etch process to remove the second hard mask layer residues, etching the plurality of semiconductor layers in the fin-shaped structure through the window portion to divide the fin-shaped structure into a first segment and a second segment, and forming an isolation feature around the first segment and the second segment.

Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.

Abstract: A method and system for producing an adjustable resistor with a set resistance for adjusting quiescent current in a GaN transistor in a power amplifier. A quiescent current on the GaN power amplifier is measured via a test probe from a microcontroller unit on a test fixture. A resistance value is determined for output of a voltage bias value to adjust the quiescent current of the GaN transistor in the power amplifier. The resistance value is stored in an electronically adjustable resistor. The adjustable resistor is coupled to an output voltage circuit to provide voltage at the voltage vias value to a voltage bias input of the power amplifier.

Abstract: A method of the present disclosure includes forming a fin-shaped structure including a plurality of semiconductor layers, a first hard mask layer, a second hard mask layer, and a third hard mask layer, forming a patterned masking layer having a mask portion and a window portion, wherein the third hard mask layer is exposed through the window portion, performing a first etch process to expose the second hard mask layer through the window portion, performing a second etch process to etch the exposed second hard mask layer and to leave behind second hard mask layer residues, performing a third etch process to remove the second hard mask layer residues, etching the plurality of semiconductor layers in the fin-shaped structure through the window portion to divide the fin-shaped structure into a first segment and a second segment, and forming an isolation feature around the first segment and the second segment.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first substrate having a first wiring structure; and a second substrate having a second wiring structure, wherein the first substrate and the second substrate are arranged side-by-side, and the first substrate and the second substrate are surrounded and separated by a molding material. The semiconductor package structure also includes a redistribution layer disposed over the first substrate and the second substrate, wherein the redistribution layer is electrically coupled to the first wiring structure and the second wiring structure; and a frame surrounding the first substrate and the second substrate.

Abstract: A machine learning method on vectorized three-dimensional models and a learning system thereof are provided. The learning system uses a computer system to perform the machine learning method using synthetic images rendered from vectorized three-dimensional models. In the method, the system acquires a computerized engineering design drawing or a stereoscopic scan file of a target object. The engineering design drawing or a stereoscopic scan file is then converted into a specific file that can be processed to render synthetic images by a rendering program. A great amount of diversified synthetic images forms a training and testing dataset for an ensemble of machine learning algorithms to train an artificial intelligence model and evaluate its accuracy.

Abstract: An apparatus for producing an ingot includes a crucible and a lid. The crucible, as a cylindrical container for accommodating a raw crystal-growing material, has an annular top edge further having an annular non-90° first guiding part. The lid provides a bottom for disposing a seed, and the bottom is furnished thereon a bottom protrusion. An outer wall of the bottom protrusion is furnished with an annular non-90° second guiding part corresponding to the first guiding part. The lid is detachable to cover the crucible by having the bottom protrusion to fit the annular the main inner wall, the first guiding part and the annular second guiding part to contact each other, and a portion of the bottom of the lid surrounding the bottom protrusion to contact the top edge of the crucible.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.

Abstract: A method for calculating parameters in a larynx image with an artificial intelligence assistance includes training a deep learning object detection software and a deep learning image recognition and segmentation software to extract a glottis image from a larynx image and recognize a membranous glottal gap; after receiving a larynx image, a plurality of larynx images captured frame-by-frame, or a larynx video that is captured when vocal folds are in a phonating state, extracting a glottis image by the deep learning object detection software; recognizing a membranous glottal gap in the glottis image and correspondingly outputting a membranous glottal gap filter by the deep learning image recognition and segmentation software; performing image processing of edge detection and image patching on the membranous glottal gap filter to clearly outline the membranous glottal gap and obtaining a medical parameter of several vocal fold anatomies from the clearly outlined membranous glottal gap.

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate including a logic region and a memory cell region. A logic device is arranged on the logic region. A memory device is arranged on the memory cell region. An isolation structure extends into a top surface of the semiconductor substrate, and laterally separates the logic region from the memory cell region. The isolation structure includes dielectric material and has an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.

Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.