Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: A host system initiates an abort of a command that has been placed into a submission queue (SQ) of the host system. The host system identifies at least one of a first outcome and a second outcome. When the first outcome indicates that the command is not completed and the second outcome indicates that the SQ entry has been fetched from the SQ, the host system sends an abort request to a storage device, and issues a cleanup request to direct the host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry based on at least one of the first outcome and the second outcome.

Abstract: A defect-reducing coating method is disclosed, which is characterized by making the coating surface of a sample face the bottom of the coating chamber, so that the sticking particles on side walls of the coating chamber will not fall on the coating surface of the sample during the coating process, thereby a smooth coating layer can be formed on the coating surface of the sample after the coating process is finished.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.

Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.

Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.

Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.

Abstract: A positioning device for a portable fitness equipment mainly provides a support frame for hanging the portable fitness equipment. The support frame includes a base and a support rod connected to each other, and there is an obtuse angle between the base and the support rod. The obtuse angle design allows the position where the support rod is connected to the base to bear less torque, which can effectively prevent the support rod from shaking or damage; and the portable fitness equipment can slide or can be fixed on the support rod, allowing users to adjust the portable fitness equipment to the most suitable height.

Abstract: A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.

Abstract: Disclosed herein is a method for decolorizing a colored polymer material, which includes subjecting the colored polymer material to a first decolorizing treatment with a first decolorizing solution to remove a colorant from the colored polymer material, so as to obtain a first decolorized polymer material and a first used decolorizing solution. A method for preparing a regenerated polymer, and a decolorizing solution are also disclosed.

Abstract: The invention disclosed herein relates to aza-quinoline compounds of Formula (I), pharmaceutical compositions comprising such compounds, and the use of such compounds for treating a disease or condition mediated by Enhancer of Zeste Homolog 2 (EZH2), Polycomb Repressive Complex 2 (PRC2), or a combination thereof.

Abstract: The present invention provides a compound of Formula (I): or an enantiomer, an enantiomeric mixture, or a pharmaceutically acceptable salt thereof; wherein the variables are as defined herein. The present invention further provides pharmaceutical compositions comprising such compounds; and methods of using such compounds for treating a disease or condition mediated by mixed lineage leukemia 1 (MLL1).

Abstract: A method of the present disclosure includes forming a fin-shaped structure including a plurality of semiconductor layers, a first hard mask layer, a second hard mask layer, and a third hard mask layer, forming a patterned masking layer having a mask portion and a window portion, wherein the third hard mask layer is exposed through the window portion, performing a first etch process to expose the second hard mask layer through the window portion, performing a second etch process to etch the exposed second hard mask layer and to leave behind second hard mask layer residues, performing a third etch process to remove the second hard mask layer residues, etching the plurality of semiconductor layers in the fin-shaped structure through the window portion to divide the fin-shaped structure into a first segment and a second segment, and forming an isolation feature around the first segment and the second segment.

Abstract: An image processing method includes the steps of lighting up at least a part of light emitting units of a light emitting device; capturing a plurality of detection images corresponding to a plurality of sections of the light emitting device respectively, wherein each section includes a plurality of lighted-up light emitting units, each detection image includes a plurality of light spots respectively corresponding to the light emitting units of the associated section, and every two adjacent sections have an overlap area including at least one lighted-up light emitting unit; and stitching the detection images of the adjacent sections together by taking the light spots corresponding to at least one lighted-up light emitting unit of the overlap area as alignment reference spots, so that the light emitting statuses of all the light emitting units are presented by a single image.

Abstract: The present invention provides a compound of Formula (I): or an enantiomer, an enantiomeric mixture, or a pharmaceutically acceptable salt thereof; wherein the variables are as defined herein. The present invention further provides pharmaceutical compositions comprising such compounds; and methods of using such compounds for treating a disease or condition mediated by mixed lineage leukemia 1 (MLL).

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.

Abstract: A light emitting element detecting method includes the steps of generating a first control signal to open a shutter of an image capturing device which captures an image toward a light outlet of a light emitting element, generating a pulse signal to light up the light emitting element, generating a second control signal to close the shutter of the image capturing device and obtaining a detection image, and determining the light emitting status of the light outlet of the light emitting element according to the detection image. As a result, the present invention can accurately detect whether the light outlet of the light emitting element has the problem of emitting no light or flashing.