Patents by Inventor Chin Liu

Chin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190006380
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Application
    Filed: October 4, 2017
    Publication date: January 3, 2019
    Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
  • SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
    Publication number: 20190006245
    Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.
    Type: Application
    Filed: August 13, 2018
    Publication date: January 3, 2019
    Inventors: Meng-Han LIN, Chih-Ren HSIEH, Chen-Chin LIU
  • Method of manufacturing a semiconductor device having deep wells
    Patent number: 10134644
    Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu
  • Method for forming micro-electro-mechanical system (MEMS) device structure
    Patent number: 10131539
    Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, and the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Han Meng, Chih-Hsien Hsu, Chia-Chi Chung, Yu-Pei Chiang, Wen-Chih Chen, Chen-Huang Huang, Zhi-Sheng Xu, Jr-Sheng Chen, Kuo-Chin Liu, Lin-Ching Huang
  • WAFER-LEVEL PACKAGE HAVING ONE DIE WITH ITS CLOCK SOURCE SHARED BY MULTIPLE DIES AND ASSOCIATED CLOCK GENERATING METHOD
    Publication number: 20180300272
    Abstract: A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.
    Type: Application
    Filed: June 26, 2018
    Publication date: October 18, 2018
    Inventors: Yi-Hung Chen, Yuan-Chin Liu
  • Semiconductor device and a method for fabricating the same
    Patent number: 10049939
    Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu
  • Operating method for inspecting equipment
    Patent number: 10048844
    Abstract: The instant disclosure provides an operating method of inspecting equipment, with the method applicable to semiconductor inspecting equipment having a movable element. The method includes: displaying a wafer graphic by a touch display; detecting a touch signal generated by the touch display; detecting the magnification of the wafer graphic when the touch signal is generated; and determining the moving speed of the movable element based on the magnification of the wafer graphic when the touch signal is generated. In addition, the moving direction of the movable element can be determined according to the touch signal. Through the instant disclosure, the operator can more intuitively operate each movable element of semiconductor inspecting equipment.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: August 14, 2018
    Assignee: MPI CORPORATION
    Inventors: Stojan Kanev, Yung-Chin Liu, Andrej Rumiantsev, Yao-Chuan Chiang
  • Wafer-level package having asynchronous FIFO buffer used to deal with data transfer between different dies and associated method
    Patent number: 10037293
    Abstract: A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: July 31, 2018
    Assignee: Nephos (Hefei) Co. Ltd.
    Inventors: Yi-Hung Chen, Yuan-Chin Liu
  • BINARY ARITHMETIC CODING APPARATUS AND METHOD
    Publication number: 20180184090
    Abstract: A binary arithmetic coding apparatus is implemented in a video encoder chip. The binary arithmetic coding apparatus outputs a code word according to a syntax element value, and includes a look-up table (LUT), a suffix generator and a combiner. The LUT outputs a first binary string according to the syntax element value. The suffix generator performs exp-Golomb binarization on the syntax element value to generate a second binary string. When the syntax element value is smaller than or equal to a threshold, the first binary string is outputted as the code word. When the syntax element value is greater than the threshold, the combiner combines the first binary string and the second binary string to form the code word.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 28, 2018
    Inventors: Pai-Chin LIU, He-Yuan LIN
  • METHOD FOR FORMING MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) DEVICE STRUCTURE
    Publication number: 20180148324
    Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, and the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.
    Type: Application
    Filed: October 5, 2017
    Publication date: May 31, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Han MENG, Chih-Hsien HSU, Chia-Chi CHUNG, Yu-Pei CHIANG, Wen-Chih CHEN, Chen-Huang HUANG, Zhi-Sheng XU, Jr-Sheng CHEN, Kuo-Chin LIU, Lin-Ching HUANG
  • Fan damping device for adjusting magnetic resistance
    Patent number: 9945383
    Abstract: A fan damping device for adjusting magnetic resistance includes: a support frame, a fan wheel, a ring-shaped magnetic core, a magnetic control unit, and a control unit. The fan blades of the fan wheel can provide air resistance, and the magnetic control unit and the control unit provide adjustable magnetic resistance. By such arrangements, resistance can be increased without increasing the size and weight of the present invention. Besides, the resistance is adjustable as desired to improve convenience of use.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: April 17, 2018
    Assignee: Keen Neek Co., Ltd.
    Inventor: Chin-Liu Wang
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING DEEP WELLS
    Publication number: 20180090392
    Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.
    Type: Application
    Filed: October 12, 2017
    Publication date: March 29, 2018
    Inventors: Meng-Han LIN, Chih-Ren HSIEH, Chen-Chin LIU
  • Charge pump circuit outputting high voltage without high voltage-endurance electric devices
    Patent number: 9917509
    Abstract: The charge pump circuit includes multiple boosting stages, and each stage includes following units. A first switch circuit is controlled by a first clock signal to couple a second terminal of a first capacitor to a first input terminal or a second input terminal. A third switch circuit is controlled by a second clock signal to couple a second terminal of a second capacitor to the first input terminal or the second input terminal. A second switch circuit is controlled by electric potentials on the second capacitor to couple a first terminal of the first capacitor to the first input terminal or an output terminal. The fourth switch circuit is controlled by electric potentials on the first capacitor to couple a first terminal of the second capacitor to the first input terminal or the output terminal.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: March 13, 2018
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Cheng-Chin Liu, Min-Hsueh Hsieh, Yung-Jie Luo
  • SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
    Publication number: 20180005897
    Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.
    Type: Application
    Filed: July 21, 2016
    Publication date: January 4, 2018
    Inventors: Meng-Han LIN, Chih-Ren HSIEH, Chen-Chin LIU
  • Cup Sleeve and Cup Assembly
    Publication number: 20180002083
    Abstract: A cup sleeve is capable of engagement with a cup lid when being sleeved around a cup. The cup lid has a sleeve engaging member. The cup sleeve includes a sleeve body formed with a receiving space for receiving the cup, and including a bottom portion, a top portion that is opposite to the bottom portion, a surrounding wall that extends from the bottom portion to the top portion, and a lid engaging unit that is formed on the surrounding wall that is proximal to the top portion for interlocking with the sleeve engaging member of the cup lid. A cup assembly is also provided.
    Type: Application
    Filed: March 23, 2017
    Publication date: January 4, 2018
    Inventor: Wen-Chin Liu
  • Semiconductor device and a method for fabricating the same
    Patent number: 9847399
    Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate. The isolation region surrounds an active region of the substrate in plan view and includes an insulating material. A first dielectric layer is formed over the active region. A mask layer is formed on at least a part of a border line between the isolation region and the active region. The mask layer covers a part, but not entirety, of the first dielectric layer and a part of the isolation region surrounding the active region. The first dielectric layer not covered by the mask layer is removed such that a part of the active region is exposed. After the first dielectric layer is removed, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. A gate electrode is formed over the gate dielectric layer.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu, Zhen Yang
  • CHARGE PUMP CIRCUIT OUTPUTTING HIGH VOLTAGE WITHOUT HIGH VOLTAGE-ENDURANCE ELECTRIC DEVICES
    Publication number: 20170346392
    Abstract: The charge pump circuit includes multiple boosting stages, and each stage includes following units. A first switch circuit is controlled by a first clock signal to couple a second terminal of a first capacitor to a first input terminal or a second input terminal. A third switch circuit is controlled by a second clock signal to couple a second terminal of a second capacitor to the first input terminal or the second input terminal. A second switch circuit is controlled by electric potentials on the second capacitor to couple a first terminal of the first capacitor to the first input terminal or an output terminal. The fourth switch circuit is controlled by electric potentials on the first capacitor to couple a first terminal of the second capacitor to the first input terminal or the output terminal.
    Type: Application
    Filed: May 26, 2016
    Publication date: November 30, 2017
    Inventors: Cheng-Chin LIU, Min-Hsueh HSIEH, Yung-Jie LUO
  • Method of manufacturing a semiconductor device having deep wells
    Patent number: 9831134
    Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu
  • ENHANCED SIGNAL AMPLITUDE IN ACOUSTIC-MAGNETOMECHANICAL EAS MARKER
    Publication number: 20170316666
    Abstract: Systems (100) and methods (600) for making a marker. The methods comprise: obtaining a resonator material which has been annealed under a tensile force selected to provide a maximum resonant amplitude at a bias field Hmax in the marker; and providing with the bias material of the marker an operating bias field Hoperating with a value less than a value of said bias field Hmax. The value of Hoperating is reduced by performing at least one of the following operations: selectively modifying a geometry of a bias material which is to be disposed in a housing of the marker; selectively modifying a spacing between the resonator material and the bias material arranged in a stacked configuration; and partially de-gaussing the bias material subsequent to being fully saturated.
    Type: Application
    Filed: July 18, 2017
    Publication date: November 2, 2017
    Inventor: Nen-chin Liu
  • Enhanced signal amplitude in acoustic-magnetomechanical EAS marker
    Patent number: 9711020
    Abstract: Systems (100) and methods (600, 1800) for making a marker. The methods comprise: obtaining a resonator material which has been annealed under a tensile force selected to provide a maximum resonant amplitude at a bias field; providing by a bias material of the marker an operating bias field with a value less than a value of the bias field; forming a first housing portion from a flexible material so as to have a planar shape; and forming a second housing portion from the flexible material so as to comprise a cavity in which the resonator and bias materials can be housed when the second housing portion is coupled to the first housing portion. The cavity is defined by two opposing short sidewalls, two opposing elongate sidewalls (OESW) and a bottom sidewall. Each of OESW is stiffened by forming a plurality of first stiffener edge features along an exterior surface thereof.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: July 18, 2017
    Assignee: Tyco Fire & Security GmbH
    Inventors: Randy J. Zirk, Gopal Chandramowle, Nen-Chin Liu