Abstract: A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.

Abstract: A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

Abstract: A portable exercise device provided includes: a base disc, two pulley assemblies, a support plate, and a fan wheel assembly. A support plate is disposed on the base disc, the two pulley assemblies are provided on the base disc, and the fan wheel assembly is provided on the support plate, so that the fan wheel assembly and the two pulley assemblies are vertically arranged on top of each other, thereby reducing the overall volume. More preferably, because the volume is reduced, the user can arbitrarily move and hang the portable exercise device at the desired position, and because the portable exercise device of the invention can be hung at different positions, which allows the user to train different muscles according to the different positions.

Abstract: An exercise device is provided, including: a main body, two fan wheels and a magnetic resistance assembly. The main body includes an axle disposed thereon. The two fan wheels are connected to the axle and rotatable relative to the main body. The magnetic resistance assembly includes two magnetoresistive rings disposed respectively on the two fan wheels and around the axle, a magnetic unit and a controlling unit. The magnetic unit includes two magnetic portions respectively corresponding to the two magnetoresistive rings. The controlling unit includes a lever rotatably disposed on the main body at a pivot point, and the magnetic unit and an operating portion are disposed on the lever and located by two opposite sides with respect to the pivot point. The pivot point and the axle are eccentrically arranged.

Abstract: A light emitting element detecting method and a light emitting element detecting equipment adapted for the method are discloses. The method includes the steps of generating a first control signal to open a shutter of an image capturing device which captures an image toward a light outlet of a light emitting element, generating a pulse signal to light up the light emitting element, generating a second control signal to close the shutter of the image capturing device and obtaining a detection image, and determining the light emitting status of the light outlet of the light emitting element according to the detection image. As a result, the present invention can accurately detect whether the light outlet of the light emitting element has the problem of emitting no light or flashing.

Abstract: An optical inspection system includes a brightness inspection module for inspecting the brightness of a light emitting element, an integrated inspection module for inspecting the near field optical characteristic and the beam quality factor of the light emitting element, and a far field inspection module for inspecting the far field optical characteristic of the light emitting element. As a result, the optical inspection system is space-saving and capable of reducing the distance and time of the movement of the device under test.

Abstract: An image processing method includes the steps of lighting up at least a part of light emitting units of a light emitting device; capturing a plurality of detection images corresponding to a plurality of sections of the light emitting device respectively, wherein each section includes a plurality of lighted-up light emitting units, each detection image includes a plurality of light spots respectively corresponding to the light emitting units of the associated section, and every two adjacent sections have an overlap area including at least one lighted-up light emitting unit; and stitching the detection images of the adjacent sections together by taking the light spots corresponding to at least one lighted-up light emitting unit of the overlap area as alignment reference spots, so that the light emitting statuses of all the light emitting units are presented by a single image.

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.

Abstract: A screw clamping device includes a body, a pressing unit, a resilient unit, a clamping unit and a connecting unit. The body is a hollow-core cylinder, is subject to axial penetration of a screwdriver, and is movable axially in synchrony with rotation of the screwdriver. The pressing unit is disposed on the body and adapted to press against a surface of a working object. The resilient unit is disposed between the body and the pressing unit. The clamping unit is rotatably connected to the body. The connecting unit has one end connected to the pressing unit and the other end connected to the clamping unit. While the body is moving axially, the connecting unit drives the clamping unit to rotate and thereby clamp or loosen screws.

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: An improved magnetoresistance adjustment device of fitness equipment suitable for using in a fan-type fitness equipment. The fitness equipment having a traction rope, and including: a resistance wheel mounted on the fitness equipment and having a wheel and an axle, the axle being mounted on the wheel; a magnetoresistive ring mounted on the resistance wheel; a fixing member fixedly mounted on the axle and having a positioning bolt, a direction of the fixing member extending to the magnetoresistive ring being a displacement direction; a displacement member having a displacement hole, a fixing portion and a magnetoresistive portion, the displacement hole allowing the positioning bolt to pass through, and the displacement member repeatedly displacing along the displacement direction to bring the magnetoresistive portion closer to or away from the magnetoresistive ring, and the fixing portion being connected to the traction rope and driven by the traction rope.

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A method for manufacturing a fluorine-free water repellent includes: mixing a paraffin, an inorganic nanopowder and a first reactive monomer to form a first mixture, in which the first reactive monomer includes a structure represented by formula (A), formula (B) or a combination thereof, the formula (A) is wherein X1 is a benzene, and the formula (B) is wherein X2 is CH3 or H and X3 is an alkyl group having 18 or more carbon atoms; mixing an emulsifier, a cosolvent and water to form a second mixture; mixing the first mixture and the second mixture to form a pre-emulsion; and adding an initiator and a second reactive monomer into the pre-emulsion, in which the first reactive monomer and the second reactive monomer are polymerized to form a water repellent, wherein the second reactive monomer is vinylidene chloride.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.

Abstract: A heat dissipation device is disclosed. The heat dissipation device includes a heat conducting plate and a heat sink. The heat conducting plate has a first surface and a second surface opposite to each other. The heat sink is coupled to the first surface of the heat conducting plate. The heat sink includes a first peak portion, a second peak portion, a valley portion and a first curved surface. The first peak portion and the second peak portion are adjacent to each other. The valley portion is located between the first peak portion and the second peak portion. The first curved surface is coupled between the first peak portion and the valley portion. An extension line perpendicular to a corresponding tangent line of the first curved surface passes between the first peak portion and the second peak portion.