Patents by Inventor Chin Liu

Chin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220359552
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
  • Publication number: 20220310498
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Inventors: Tzu-Hung LIN, Yuan-Chin LIU
  • Patent number: 11451714
    Abstract: A light emitting element detecting method includes the steps of generating a first control signal to open a shutter of an image capturing device which captures an image toward a light outlet of a light emitting element, generating a pulse signal to light up the light emitting element, generating a second control signal to close the shutter of the image capturing device and obtaining a detection image, and determining the light emitting status of the light outlet of the light emitting element according to the detection image. As a result, the present invention can accurately detect whether the light outlet of the light emitting element has the problem of emitting no light or flashing.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: September 20, 2022
    Assignee: MPI CORPORATION
    Inventors: Ping-Ying Wu, Yung-Chin Liu, Hsuan-Chiao Huang
  • Publication number: 20220289732
    Abstract: The present invention provides compounds of Formula (I) or a pharmaceutically acceptable salt thereof; (I) which are inhibitors of WDR5. The present invention also provides pharmaceutical compositions comprising such compounds, compositions comprising such compounds with an additional therapeutic agent and the therapeutic uses of such compounds.
    Type: Application
    Filed: August 7, 2020
    Publication date: September 15, 2022
    Inventors: Lichao FANG, Zhenting GAO, Xiangqing JIANG, Kevin Kun Chin LIU, Sing Yeung Frankie MAK, Counde OYANG, Ce WANG, Tao WANG, Jianping WU, Wu YINGMING, Qitao XIAO
  • Publication number: 20220280509
    Abstract: Provided aza-quinoline compounds of Formula (I), pharmaceutical compositions comprising such compounds; and the use of such compounds for treating a disease or condition mediate by Enhancer of Zeste Homolog 2 (EZH2), Polycomb Repressive Complex 2 (PRC2), or a combination thereof.
    Type: Application
    Filed: September 24, 2020
    Publication date: September 8, 2022
    Inventors: Ling LI, Xuan DAI, Michael DORE, Xiang-Ju Justin GU, Kevin Kun Chin LIU, Sing Yeung Frankie MAK, Yuan MI, Counde OYANG, Julien PAPILLON, Wei (Vicky) QI, Xiaoxia YAN, Zhengtian YU, Ji Yue (Jeff) ZHANG, Kehao ZHAO
  • Patent number: 11430799
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
  • Patent number: 11387176
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: July 12, 2022
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Yuan-Chin Liu
  • Publication number: 20220184451
    Abstract: A positioning device for a portable fitness equipment mainly provides a support frame for hanging the portable fitness equipment. The support frame includes a base and a support rod connected to each other, and there is an obtuse angle between the base and the support rod. The obtuse angle design allows the position where the support rod is connected to the base to bear less torque, which can effectively prevent the support rod from shaking or damage; and the portable fitness equipment can slide or can be fixed on the support rod, allowing users to adjust the portable fitness equipment to the most suitable height.
    Type: Application
    Filed: July 23, 2021
    Publication date: June 16, 2022
    Inventor: Chin-Liu Wang
  • Patent number: 11346789
    Abstract: An optical inspection system includes a brightness inspection module for inspecting the brightness of a light emitting element, an integrated inspection module for inspecting the near field optical characteristic and the beam quality factor of the light emitting element, and a far field inspection module for inspecting the far field optical characteristic of the light emitting element. As a result, the optical inspection system is space-saving and capable of reducing the distance and time of the movement of the device under test.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: May 31, 2022
    Assignee: MPI CORPORATION
    Inventors: Ping-Ying Wu, Chiu-Wang Chen, Yung-Chin Liu
  • Publication number: 20220127794
    Abstract: A track mounting structure includes: a linear motor coil, a linear motor magnet correspondingly provided with the linear motor coil, a first track, and a trolley; wherein, the cross-section of the trolley is U-shape, the internal of the U-shape forms a mounting cavity; the first track is provided inside the mounting cavity, two groups of upper rollers being axis crossing are provided between an upper surface of the first track and an upper surface of the mounting cavity. The disclosure moves the track beneath the linear motor coil, thus increasing the available space, which can be used to increase the size and load of the trolley, so as to achieve the purpose of changing the track form and strengthening the track structure.
    Type: Application
    Filed: November 23, 2020
    Publication date: April 28, 2022
    Inventors: YUAN-CHIN LIU, MING-RONG GU
  • Patent number: 11264292
    Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
  • Patent number: 11240906
    Abstract: A circuit board heat dissipation system includes circuit board unit that includes a motherboard and a daughterboard, a base seat, and a fastening unit that includes a plurality of first and second fastening components. Each first fastening component extends through the daughterboard and is engaged with the base seat. Each second fastening component includes a long fastener that extends through the base seat and the daughterboard and that is engaged with the motherboard, and a flat washer and a resilient member that are sleeved on the long fastener. The resilient member is disposed between a head portion of the long fastener and the flat washer for biasing the base seat and the daughterboard against the motherboard.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: February 1, 2022
    Assignee: ADVANTECH CO., LTD.
    Inventors: Yu-Chin Liu, Wen-Yuan Yi
  • Publication number: 20220005721
    Abstract: A method of aligning a wafer includes defining a reference direction for aligning the wafer; capturing an image of the wafer held on a chuck; using an identifying module to analyze a straight line on the image of the wafer; calculating an offset angle between the straight line and the reference direction; and calibrating the offset angle to align the straight line with the reference direction by way rotating the chuck.
    Type: Application
    Filed: July 2, 2020
    Publication date: January 6, 2022
    Inventors: Yung-Chin LIU, Chien-Hung CHEN, Men-Han LEE
  • Patent number: 11215408
    Abstract: A heat dissipation device includes a heat conducting plate and a heat sink. The heat conducting plate has a first surface and a second surface opposite to each other. The heat sink is coupled to the first surface of the heat conducting plate. The heat sink includes a first peak portion, a second peak portion, a valley portion and a first curved surface. The first peak portion and the second peak portion are adjacent to each other. The valley portion is located between the first peak portion and the second peak portion. The first curved surface is coupled between the first peak portion and the valley portion. An extension line perpendicular to a corresponding tangent line of the first curved surface passes between the first peak portion and the second peak portion.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: January 4, 2022
    Assignee: AVERMEDIA TECHNOLOGIES, INC.
    Inventors: Jui-Hung Kao, Yu-Chin Liu, Wen-Tse Yan
  • Patent number: 11195834
    Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: December 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu
  • Patent number: 11191990
    Abstract: A portable exercise device provided includes: a base disc, two pulley assemblies, a support plate, and a fan wheel assembly. A support plate is disposed on the base disc, the two pulley assemblies are provided on the base disc, and the fan wheel assembly is provided on the support plate, so that the fan wheel assembly and the two pulley assemblies are vertically arranged on top of each other, thereby reducing the overall volume. More preferably, because the volume is reduced, the user can arbitrarily move and hang the portable exercise device at the desired position, and because the portable exercise device of the invention can be hung at different positions, which allows the user to train different muscles according to the different positions.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: December 7, 2021
    Assignee: C2P (Taiwan) Ltd.
    Inventor: Chin-Liu Wang
  • Publication number: 20210366909
    Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.
    Type: Application
    Filed: March 9, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Duen-Huei Hou, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu, J.H. Wang
  • Publication number: 20210352799
    Abstract: A circuit board heat dissipation system includes circuit board unit that includes a motherboard and a daughterboard, a base seat, and a fastening unit that includes a plurality of first and second fastening components. Each first fastening component extends through the daughterboard and is engaged with the base seat. Each second fastening component includes a long fastener that extends through the base seat and the daughterboard and that is engaged with the motherboard, and a flat washer and a resilient member that are sleeved on the long fastener. The resilient member is disposed between a head portion of the long fastener and the flat washer for biasing the base seat and the daughterboard against the motherboard.
    Type: Application
    Filed: December 3, 2020
    Publication date: November 11, 2021
    Inventors: Yu-Chin LIU, Wen-Yuan YI
  • Publication number: 20210325788
    Abstract: A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Alexander YPMA, Cyrus Emil TABERY, Simon Hendrik Celine VAN GORP, Chenxi LIN, Dag SONNTAG, Hakki Ergün CEKLI, Ruben ALVAREZ SANCHEZ, Shih-Chin LIU, Simon Philip Spencer HASTINGS, Boris MENCHTCHIKOV, Christiaan Theodoor DE RUITER, Peter TEN BERGE, Michael James LERCEL, Wei DUAN, Pierre-Yves Jerome Yvan GUITTET
  • Patent number: 11147998
    Abstract: An exercise device is provided, including: a main body, two fan wheels and a magnetic resistance assembly. The main body includes an axle disposed thereon. The two fan wheels are connected to the axle and rotatable relative to the main body. The magnetic resistance assembly includes two magnetoresistive rings disposed respectively on the two fan wheels and around the axle, a magnetic unit and a controlling unit. The magnetic unit includes two magnetic portions respectively corresponding to the two magnetoresistive rings. The controlling unit includes a lever rotatably disposed on the main body at a pivot point, and the magnetic unit and an operating portion are disposed on the lever and located by two opposite sides with respect to the pivot point. The pivot point and the axle are eccentrically arranged.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: October 19, 2021
    Assignee: C2P (TAIWAN) LTD.
    Inventor: Chin-Liu Wang