Abstract: An aligning method for use in semiconductor inspection apparatus is provided. The semiconductor inspection apparatus includes a stage and a touch-control screen. The aligning method includes defining a reference direction; displaying an image of a device under test supported by the stage on the touch-control screen; detecting a first touch point and a second touch point occurred on the touch-control screen; defining a straight line according to the first touch point and the second touch point; calculating an included angle defined by the straight and the reference direction; and rotating the stage according to the included angle.

Abstract: A multi-axial unidirectional power transmission system includes a transmission unit and a resistance unit. The transmission unit includes a first main shaft and a transmission wheel provided on the first main shaft. The resistance unit includes a second main shaft and a damping wheel mounted on the second main shaft. The two transmission wheels and the damping wheel can be placed flat on the body since they are mounted on different main shafts, thereby making the whole plane of the multi-axis unidirectional power transmission system consistent, thus achieving the effects of space saving, convenient storage and convenient transportation.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

Abstract: A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

Abstract: A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.

Abstract: A dynamic panoramic image parameter adjustment system and a method thereof are provided. The dynamic panoramic image parameter adjustment system includes a plurality of image capture elements and a parameter processing module. Firstly, a plurality of first images is captured by the image capture elements at a first time point. A plurality of first parameter setting values corresponding to the image capture elements are extracted by the parameter processing module. The parameter processing module calculates element compensation values based on the first parameter setting values and the target setting values, and compensates the first parameter setting values by using the element compensation values to form the second parameter setting values. Finally, the first parameter setting values are adjusted as the second parameter setting values at a second time point and a plurality of second images for forming a dynamic panoramic image together with the first images are captured.

Abstract: A multi-axial unidirectional power transmission system includes a transmission unit and a resistance unit. The transmission unit includes a first main shaft and a transmission wheel provided on the first main shaft. The resistance unit includes a second main shaft and a damping wheel mounted on the second main shaft. The two transmission wheels and the damping wheel can be placed flat on the body since they are mounted on different main shafts, thereby making the whole plane of the multi-axis unidirectional power transmission system consistent, thus achieving the effects of space saving, convenient storage and convenient transportation.

Abstract: An aligning method for use in semiconductor inspection apparatus is provided. The semiconductor inspection apparatus includes a stage and a touch-control screen. The aligning method includes defining a reference direction; displaying an image of a device under test supported by the stage on the touch-control screen; detecting a first touch point and a second touch point occurred on the touch-control screen; defining a straight line according to the first touch point and the second touch point; calculating an included angle defined by the straight and the reference direction; and rotating the stage according to the included angle.

Abstract: A dynamic panoramic image parameter adjustment system and a method thereof are provided. The dynamic panoramic image parameter adjustment system includes a plurality of image capture elements and a parameter processing module. Firstly, a plurality of first images is captured by the image capture elements at a first time point. A plurality of first parameter setting values corresponding to the image capture elements are extracted by the parameter processing module. The parameter processing module calculates element compensation values based on the first parameter setting values and the target setting values, and compensates the first parameter setting values by using the element compensation values to form the second parameter setting values. Finally, the first parameter setting values are adjusted as the second parameter setting values at a second time point and a plurality of second images for forming a dynamic panoramic image together with the first images are captured.

Abstract: A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.

Abstract: A screw clamping device includes a body, a pressing unit, a resilient unit, a clamping unit and a connecting unit. The body is a hollow-core cylinder, is subject to axial penetration of a screwdriver, and is movable axially in synchrony with rotation of the screwdriver. The pressing unit is disposed on the body and adapted to press against a surface of a working object. The resilient unit is disposed between the body and the pressing unit. The clamping unit is rotatably connected to the body. The connecting unit has one end connected to the pressing unit and the other end connected to the clamping unit. While the body is moving axially, the connecting unit drives the clamping unit to rotate and thereby clamp or loosen screws.

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

Abstract: An improved magnetoresistance adjustment device of fitness equipment suitable for using in a fan-type fitness equipment. The fitness equipment being disposed with a traction rope, and comprising: a resistance wheel mounted on the fitness equipment and having a wheel and an axle, the axle being mounted on the wheel; a magnetoresistive ring mounted on the resistance wheel; a fixing member fixedly mounted on the axle and being disposed with a positioning bolt, a direction of the fixing member extending to the magnetoresistive ring being a displacement direction; a displacement member having a displacement hole, a fixing portion and a magnetoresistive portion, the displacement hole allowing the positioning bolt to pass through, and the displacement member repeatedly displacing along the displacement direction to bring the magnetoresistive portion closer to or away from the magnetoresistive ring, and the fixing portion being connected to the traction rope and driven by the traction rope.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.