Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel region and a periphery region, forming a light sensing element on the pixel region, and forming at least one transistor in the pixel region and at least one transistor in the periphery region. The step of forming the at least one transistor in the pixel region and periphery region includes forming a gate electrode in the pixel region and periphery region, depositing a dielectric layer over the pixel region and periphery region, partially etching the dielectric layer to form sidewall spacers on the gate electrode and leaving a portion of the dielectric layer overlying the pixel region, and forming source/drain (S/D) regions by ion implantation.

Abstract: A flower pot having a removable base, comprising: a basin-shaped main body, with its bottom portion or side wall provided with at least an opening, and at least a female connection piece disposed on said basin-shaped main body and around perimeter of said opening; and at least a removable base, having a male connection piece disposed thereon corresponding to said female connection piece, such that the removable base penetrates through said opening and is connected to said basin-shaped main body through connecting said male connection piece to said female connection piece. When a plant in said flower pot has grown up to a certain extent and requires more space, said removable base can be removed, such that the roots of a plant in said flower pot may grow and expand through said opening to a new flower pot, hereby saving the effort and trouble of transplanting.

Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel region and a periphery region, forming a light sensing element on the pixel region, and forming at least one transistor in the pixel region and at least one transistor in the periphery region. The step of forming the at least one transistor in the pixel region and periphery region includes forming a gate electrode in the pixel region and periphery region, depositing a dielectric layer over the pixel region and periphery region, partially etching the dielectric layer to form sidewall spacers on the gate electrode and leaving a portion of the dielectric layer overlying the pixel region, and forming source/drain (S/D) regions by ion implantation.

Abstract: The present invention relates to a process for preparing a precursor solution for polyimide/silica composite material and a process for forming a polyimide/silica composite material film on a substrate, comprising adding a monomer of a silane compound to allow a poly(amic acid) to carry a silica moiety; adding a monomer of formula (R6)xSi(R7)(4-x) to allow the silica moiety to carry a photo-polymerizable unsaturated group; and adding a monomer of formula R8N(R9)2 to allow the poly(amic acid) to carry a photo-polymerizable unsaturated group, where R6, R7, R8, R9, and x are as defined in the specification. The present invention also relates to a precursor solution for polyimide/silica composite material and a polyimide/silica composite material. The composite material of the present invention is useful in microelectronic devices, semiconductor elements, and photoelectric elements.

Abstract: A system and a method of multi-objective capacity planning in the TFT-LCD panel manufacturing industry are provided. The system includes a capacity planning module and a multi-objective planning module. In the present method, a capacity planning plan corresponding to different objective is evaluated by the capacity planning module. A set of constraints of each objective is established by the multi-objective planning module according to characteristic parameters, so as to optimize the objective. Then, the optimized objectives are drawn into a graph to select an appropriate capacity planning plan.

Abstract: A process for preparing a precursor solution for polyimide/silica composite material and a process for forming a polyimide/silica composite material film on a substrate, including adding a monomer of a silane compound to allow a poly(amic acid) to carry a silica moiety; adding a monomer of formula (R6)xSi(R7)(4?x) to allow the silica moiety to carry a photo-polymerizable unsaturated group; and adding a monomer of formula R8N(R9)2 to allow the poly(amic acid) to carry a photo-polymerizable unsaturated group, where R6, R7, R8, R9, and x are as defined in the specification. Also, a precursor solution for polyimide/silica composite material and a polyimide/silica composite material. The composite material is useful in microelectronic devices, semiconductor elements, and photoelectric elements.

Abstract: A semiconductor device is disclosed. The semiconductor device provides a substrate comprising an image sensor region and a circuit region, wherein the circuit region comprises a pad region and a connecting region. A multilayer interconnect structure is formed on the substrate, wherein the multilayer interconnect structure comprises a plurality of dielectric layers, a plurality of lower wirings at the pad region and the connecting region, and a top wiring on at least one of the lower wirings at the connecting region. A passivation layer is formed over the multilayer interconnect structure. A pad structure is formed through the passivation layer and at least one of the dielectric layers on and electrically connected to at least one of the lower wirings at the pad region.

Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.

Abstract: The present invention discloses a method of fabricating organic light emitting diode array, which adopts a directional spin coating technology to grow different organic light-emitting materials on the same plane so as to control the color of the emitted light and accomplish monochrome or full color organic light emitting diodes.

Abstract: An image sensor array includes a substrate having at least three image sensors located therein. The image sensor array also includes a blue filter positioned proximate to the first image sensor; a green filter proximate to the second image sensor; and a red filter proximate to the third image sensor. A first microlens is positionally arranged with the blue filter and the first image sensor; a second microlens is positionally arranged with the green filter and the second image sensor; and a third microlens is positionally arranged with the red filter and the third image sensor. The first microlens has a larger effective area than the second microlens, and the second microlens has a larger effective area than the third microlens.

Abstract: An integrated circuit structure includes a substrate and a metallization layer over the substrate. The metallization layer includes a dielectric layer and metal lines in the dielectric layer. The integrated circuit structure further includes a sensing element over the metallization layer. The sensing element may be formed in passivation layers.

Abstract: An image sensor device includes a semiconductor substrate having a front surface and a back surface; an array of pixels formed on the front surface of the semiconductor substrate, each pixel being adapted for sensing light radiation; an array of color filters formed over the plurality of pixels, each color filter being adapted for allowing a wavelength of light radiation to reach at least one of the plurality of pixels; and an array of micro-lens formed over the array of color filters, each micro-lens being adapted for directing light radiation to at least one of the color filters in the array. The array of color filters includes structure adapted for blocking light radiation that is traveling towards a region between adjacent micro-lens.

Abstract: An image sensor array includes a substrate having at least three image sensors located therein. The image sensor array also includes a blue filter positioned proximate to the first image sensor; a green filter proximate to the second image sensor; and a red filter proximate to the third image sensor. A first microlens is positionally arranged with the blue filter and the first image sensor; a second microlens is positionally arranged with the green filter and the second image sensor; and a third microlens is positionally arranged with the red filter and the third image sensor. The first microlens has a larger effective area than the second microlens, and the second microlens has a larger effective area than the third microlens.

Abstract: An image sensor array includes a substrate having at least three image sensors located therein. The image sensor array also includes a blue filter positioned proximate to the first image sensor; a green filter proximate to the second image sensor; and a red filter proximate to the third image sensor A first microlens is positionally arranged with the blue filter and the first image sensor; a second microlens is positionally arranged with the green filter and the second image sensor; and a third microlens is positionally arranged with the red filter and the third image sensor. The first microlens has a larger effective area than the second microlens, and the second microlens has a larger effective area than the third microlens.

Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.

Abstract: An electricity-saving type infrared electronic lock core is disclosed herein, which includes a body, an infrared sensor, a radio frequency identification system and a power supplier. The infrared sensor is disposed on one end of the body and includes an infrared receiver-transmitter, and the radio frequency identification system is electrically connected with the infrared sensor, the power supplier and the relative elements for unlocking the body. When the infrared sensor detects a person or an object within the scheduled area, the radio frequency identification system can identify it and further drive the relative elements for unlocking the body if the identification is correct. But when the infrared sensor does not detect a person or an object, the radio frequency identification system enters into an electricity-saving mode for saving the electric power.

Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel region and a periphery region, forming a light sensing element on the pixel region, and forming at least one transistor in the pixel region and at least one transistor in the periphery region. The step of forming the at least one transistor in the pixel region and periphery region includes forming a gate electrode in the pixel region and periphery region, depositing a dielectric layer over the pixel region and periphery region, partially etching the dielectric layer to form sidewall spacers on the gate electrode and leaving a portion of the dielectric layer overlying the pixel region, and forming source/drain (S/D) regions by ion implantation.

Abstract: A semiconductor device is disclosed. The semiconductor device provides a substrate comprising an image sensor region and a circuit region, wherein the circuit region comprises a pad region and a connecting region. A multilayer interconnect structure is formed on the substrate, wherein the multilayer interconnect structure comprises a plurality of dielectric layers, a plurality of lower wirings at the pad region and the connecting region, and a top wiring on at least one of the lower wirings at the connecting region. A passivation layer is formed over the multilayer interconnect structure. A pad structure is formed through the passivation layer and at least one of the dielectric layers on and electrically connected to at least one of the lower wirings at the pad region.

Abstract: An image sensor array includes a substrate having at least three image sensors located therein. The image sensor array also includes a blue filter positioned proximate to the first image sensor; a green filter proximate to the second image sensor; and a red filter proximate to the third image sensor A first microlens is positionally arranged with the blue filter and the first image sensor; a second microlens is positionally arranged with the green filter and the second image sensor; and a third microlens is positionally arranged with the red filter and the third image sensor. The first microlens has a larger effective area than the second microlens, and the second microlens has a larger effective area than the third microlens.

Abstract: CMOS image sensor devices and fabrication methods thereof. A CMOS image sensor device comprises an array of photo-sensing pixels in a first region of a substrate. Each photo-sensing pixel comprises a fully non-salicide transistor and a pinned photodiode. A logic circuit comprises a complementary metal oxide semiconductor (CMOS) transistor in a second region of the substrate, wherein a salicide is formed on the CMOS transistor in the second region but non-salicide is formed on the first region of the substrate.