Abstract: A semiconductor structure includes a first substrate, a second substrate, a first sensing structure over the first substrate, and between the first substrate and the second substrate, a via extending through the second substrate, and a second sensing structure over the second substrate, and including an interconnect structure electrically connected with the via, and a sensing material at least partially covering the interconnect structure.

Abstract: A syringe is applied to connect with a vial and a needle, and the syringe includes an outer protecting housing, a connecting ring, a vial housing, an inner tube, a bidirectional guiding tube device, a screwing sleeve, a ratchet, a spiral rotating rod and an injection rod unit. The connecting ring is mounted on a front end of the outer protecting housing, and the vial housing is connected with the connecting ring for assembling a vial. The inner tube, the bidirectional guiding tube device, the screwing sleeve, the ratchet, the spiral rotating rod and the injection rod unit are mounted in the outer protecting housing. The injection rod unit is rapidly pulled backward and then is pressed to move forward for injecting.

Abstract: In accordance with some embodiments, a method and an apparatus for baking photoresist patterns are provided. The method includes putting a wafer over a heating assembly. A photoresist pattern is formed over a top surface of the wafer. The method further includes curing the wafer from the top surface of the wafer by a curing assembly while heating the wafer from a bottom surface of the wafer by a heating assembly.

Abstract: An image sensor device includes a semiconductor substrate having a front surface and a back surface; an array of pixels formed on the front surface of the semiconductor substrate, each pixel being adapted for sensing light radiation; an array of color filters formed over the plurality of pixels, each color filter being adapted for allowing a wavelength of light radiation to reach at least one of the plurality of pixels; and an array of micro-lens formed over the array of color filters, each micro-lens being adapted for directing light radiation to at least one of the color filters in the array. The array of color filters includes structure adapted for blocking light radiation that is traveling towards a region between adjacent micro-lens.

Abstract: There is provided a nanoparticle-containing hydrogel comprising metal nanoparticles and at least one peptide. The nanoparticle-containing hydrogel may possess antibacterial activity. There is also provided a method for preparing the nanoparticle-containing hydrogel, and compositions and uses thereof.

Abstract: The present invention discloses a indenotriphenylene-based amine derivative is represented by the following formula (A), the organic EL device employing the compound as hole transport material, electron blocking material, can lower driving voltage and power consumption, increasing efficiency and half-life time. Wherein R1 to R5, m, n, p, L and Ar are the same definition as described in the present invention.

Abstract: The present invention generally discloses an organic optoelectronic material and organic electroluminescent (herein referred to as organic EL) device, organic photovoltaics (herein referred to as OPV) device and organic thin-film transistor (herein referred to as OTFT) device using the organic optoelectronic material. More specifically, the present invention relates to the organic optoelectronic material formula (1), and an organic EL device, OPV device and OTFT device employing the organic optoelectronic material can improve performance.

Abstract: The present invention discloses a novel phenanthroline-based compound is represented by the following formula (I), the organic EL device employing the phenanthroline-based compound as hole blocking material/electron transport material or phosphorescent host can display good performance. L, m, n, X, Y and R1 to R20 each have the same meaning as described in the present invention.

Abstract: Some embodiments relate to multiple MEMS devices that are integrated together on a single substrate. A device substrate comprising first and second micro-electro mechanical system (MEMS) devices is bonded to a capping structure. The capping structure comprises a first cavity arranged over the first MEMS device and a second cavity arranged over the second MEMS device. The first cavity is filled with a first gas at a first gas pressure. The second cavity is filled with a second gas at a second gas pressure, which is different from the first gas pressure. A recess is arranged within a lower surface of the capping structure. The recess abuts the second cavity. A vent is arranged within the capping structure. The vent extends from a top of the recess to the upper surface of the capping structure. A lid is arranged within the vent and configured to seal the second cavity.

Abstract: A power saving circuit for an electronic device is disclosed. The power saving circuit includes a direct-current (DC) power supply, a sensing unit, and a control unit. The DC power supply is used for providing a DC current. The sensing unit, coupled to the DC power supply, is used for detecting the DC current and operating to generate a voltage signal according to the DC current. The control unit, coupled to the sensing unit, is used for determining whether a system circuit of the electronic device has a light load or a heavy load and generating an enable signal.

Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

Abstract: A data protecting method for protecting a sub-directory and at least one pre-stored file in a rewritable non-volatile memory module is provided. The method includes receiving a write command from a host system and determining whether a write address indicated by the write command is an address storing a file description block of the sub-directory. The method also includes, when the write address is the address storing a file description block of the sub-directory, determining whether a portion of data streams corresponding to the write command is the same as a corresponding content recorded in the file description block of the sub-directory. The method further includes, when the portion of data streams corresponding to the write command is not the same as the corresponding content recorded in the file description block of the sub-directory, transmitting a write failure signal to the host system.

Abstract: Provided is an integrated circuit (IC) photo mask. The IC photo mask includes a main feature of the IC, the main feature having a plurality of sides, and a plurality of assist features, the assist features being spaced from each other and spaced from the main feature, wherein each one of the assist features is adjacent to one of the sides, each one of the assist features has an elongated shape along a direction, whereby extending the shape in the direction would intersect at least another one of the assist features and the assist features are sub-resolution correction features for correcting for optical proximity effect in a photolithography process.

Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

Abstract: A method for detecting touch points of multi-type objects is provided and includes the steps: detecting a plurality of touch points existing and referring the touch points as a first-type touch point or a second-type touch point according to an energy variation above a first effective value and below a second effective value or above the second effective value; if there exists at least one of the touch points not being referred as the first-type touch point or the second-type touch point, detecting an area size of the non-referred touch point and referring the non-referred touch point as the first-type touch point or the second type touch point if the area size of the non-referred touch point is smaller or larger than a first predetermined value; scanning and determining coordinate positions of the first-type touch point and the second-type touch point by performing a magnifying operation, respectively.

Abstract: In accordance with some embodiments, a method and an apparatus for baking photoresist patterns are provided. The method includes putting a wafer over a heating assembly. A photoresist pattern is formed over a top surface of the wafer. The method further includes curing the wafer from the top surface of the wafer by a curing assembly while heating the wafer from a bottom surface of the wafer by a heating assembly.

Abstract: A semiconductor device includes a device substrate and a conductive capping substrate. The device substrate includes at least one micro-electro mechanical system (MEMS) device. The conductive capping substrate is bonded to the device substrate and includes a cap portion covering the MEMS device, and a conductor portion in electrical contact with the device substrate.

Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

Abstract: One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.