Patents by Inventor Chin Yu

Chin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250136686
    Abstract: The present disclosure provides a method for treating a disease with an inhibitor for inhibiting expression and/or activity of CD101, and in particular a method for treating cancer, an inflammatory or infectious disease, an autoimmune disease, or an endocrine disease. The present disclosure also provides an antibody specifically binding to CD101, a nucleic acid encoding the antibody, a vector including the nucleic acid, and a host cell including the nucleic acid or the vector. The present disclosure also provides a pharmaceutical composition including the antibody, and a use of the antibody and the pharmaceutical composition.
    Type: Application
    Filed: December 30, 2024
    Publication date: May 1, 2025
    Inventors: Hung Yan Lau, Chin Yu Li
  • Publication number: 20250122278
    Abstract: The present disclosure provides an antibody specifically binding to interleukin-9 (IL-9), a nucleic acid encoding the antibody, a vector including the nucleic acid, a host cell including the nucleic acid or the vector, a pharmaceutical composition including the antibody, and a use of the antibody and the pharmaceutical composition.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Inventors: Hung Yan Lau, Chin Yu Li
  • Patent number: 12266593
    Abstract: A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Li Yang, Wen-Hsiung Lu, Jhao-Yi Wang, Fu Wei Liu, Chin-Yu Ku
  • Publication number: 20250071984
    Abstract: A memory device includes a memory cell having a transistor and a resistor coupled to each other, where the memory cell is on the first side, and the transistor further includes a plurality of first sub-transistors disposed in a first region of the substate. The memory device includes a plurality of second sub-transistors disposed in a second region of the substrate. The memory device further includes a first interconnect structure disposed on the second side. The first sub-transistors are each coupled to the first interconnect structure through a plurality of first via structures. The second sub-transistors are each coupled to the first interconnect structure through a plurality of second via structures and at least a third via structure, where the first via structures and the second via structures each have a first cross-sectional area, and the third via structure has a second cross-sectional area that is different from the first cross-sectional area.
    Type: Application
    Filed: January 11, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Li-Chin Yu, Meng-Sheng Chang
  • Patent number: 12238939
    Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Fei Chiu, Yong-Shiuan Tsair, Wen-Ting Chu, Yu-Wen Liao, Chin-Yu Mei, Po-Hao Tseng
  • Patent number: 12237317
    Abstract: A LED device includes multiple LED chips each including opposite first and second surfaces, a side surface, and an electrode assembly disposed on the second surface and including first and second electrodes. The first surface of each of the LED chips is a light exit surface. The LED device further includes an electric circuit layer assembly disposed on the second surfaces of the LED chips and having opposite first and second surfaces and a side surface. The first surface is electrically connected to the first and second electrodes. The LED device further includes an encapsulating layer enclosing the LED chips and the electric circuit layer assembly to expose the second surface of the electric circuit layer assembly.
    Type: Grant
    Filed: May 21, 2024
    Date of Patent: February 25, 2025
    Assignee: QUANZHOU SAN'AN SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Junpeng Shi, Chen-Ke Hsu, Chang-Chin Yu, Yanqiu Liao, Zhenduan Lin, Zhaowu Huang, Senpeng Huang
  • Patent number: 12226581
    Abstract: A headgear assembly includes a strap of a first flexible material with an elongate edge, and a second flexible material folded around and running along the elongate edge. The second flexible material may be an elastic material. The second flexible material may also cover an intersection or joint in the first flexible material such that the first flexible material may be made from two flexible materials layered together or joined end to end.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: February 18, 2025
    Assignee: ResMed Pty Ltd
    Inventors: Michiel Kooij, Rupert Christian Scheiner, Annie Yu, Tzu-Chin Yu, Kit Lun Yick, Yiu Wan Yip, Jessica Lea Dunn
  • Publication number: 20250048943
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material on a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An insulating structure is arranged over and along opposing outermost sidewalls of the top electrode. The bottom electrode laterally extends to different non-zero distances past opposing outermost sidewalls of the insulating structure.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: Chieh-Fei Chiu, Wen-Ting Chu, Yong-Shiuan Tsair, Yu-Wen Liao, Chin-Yu Mei, Po-Hao Tseng
  • Publication number: 20250032621
    Abstract: A drug conjugate includes a structure shown by the following formula: Z-(linker-[R]m)n. In the formula, Z is a drug compound, R is a sugar, and m and n are independently an integer from 1 to 6. The drug compound Z is a hepatitis virus targeting drug, a hepatitis B virus (HBV) drug, an inhibitor of apoptosis protein (IAP) antagonist, a multidrug resistance (MDR) inhibitor, or analogues, precursors, prodrugs, derivatives thereof.
    Type: Application
    Filed: May 30, 2024
    Publication date: January 30, 2025
    Applicant: SeeCure Taiwan Co., Ltd.
    Inventors: Wuu-Jyh Lin, Min-Ching Chung, Chi-Shiang Ke, Ya-Chen Tseng, Chin-Yu Liang, Yen-Chun Lee, Hsin-Jou Li, Tai-Yun Huang, Nai-Chen Hsueh, Yan-Feng Jiang
  • Patent number: 12209013
    Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.
    Type: Grant
    Filed: August 6, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jhao-Yi Wang, Chin-Yu Ku, Wen-Hsiung Lu, Lung-Kai Mao, Ming-Da Cheng
  • Publication number: 20250026042
    Abstract: A method of slicing wafers from a monocrystalline semiconductor ingot includes attaching a circumferential edge of the ingot to a bond beam and positioning sacrificial disks adjacent longitudinal end faces of the ingot. One sacrificial disk is positioned adjacent each of the longitudinal end faces. The method also includes connecting the bond beam to a wire saw that includes a wire web and performing a slicing operation on the ingot by operating the wire saw to drive the wire web and move the bond beam and the ingot in a movement direction towards the wire web to slice the wafers from the ingot.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventors: Jung-Chiang Liao, Yi-Chun Chou, Liang-Chin Chen, Chin-Yu Chang, Ming-Tao Chia, Peter D. Albrecht
  • Publication number: 20250026847
    Abstract: The present invention relates to administration speed of obinutuzumab.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 23, 2025
    Inventors: Michael WENGER, Mehrdad MOBASHER, Chin-Yu LIN
  • Publication number: 20250025951
    Abstract: A system for slicing wafers from a monocrystalline semiconductor ingot includes a wire saw, a bond beam, the monocrystalline semiconductor ingot, and two sacrificial disks. The wire saw includes a wire web and wire guides operable to drive the wire web during a slicing operation. The bond beam is connected to the wire saw. The wire saw is operable to move the bond beam in a movement direction towards the wire web during the slicing operation to slice the wafers from the ingot. The ingot includes longitudinal end faces and a circumferential edge extending between the longitudinal end faces. The ingot is attached to the bond beam along the circumferential edge. One sacrificial disk is positioned adjacent each of the longitudinal end faces of the ingot to inhibit uncontrolled breakage of the wafers during the slicing operation.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventors: Jung-Chiang Liao, Yi-Chun Chou, Liang-Chin Chen, Chin-Yu Chang, Ming-Tao Chia, Peter D. Albrecht
  • Patent number: 12194322
    Abstract: A personal entertainment respiratory apparatus provides air to a user to provide a fully immersive entertainment experience. The personal entertainment system may comprise a flow generator for providing the flow of air. A personal spatial respiratory interface may be coupled to the flow generator. The personal spatial respiratory interface may comprise an outlet for the flow generator. The personal spatial respiratory interface may further be configured to direct the flow of air within an ambient breathing proximity of a user. The personal entertainment respiratory apparatus may further comprise a controller and a sensory particle dispenser. The controller and sensory particle dispenser may be configured to selectively activate release of a sensory particle from the dispenser into the directed flow of air in response to an entertainment triggering signal.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: January 14, 2025
    Assignee: ResMed Pty Ltd
    Inventors: Tzu-Chin Yu, Emma Anne Connell, David Creusot, Donald Darkin, Barton John Kenyon, Paul Jan Klasek, Andrew Sims, Quangang Yang, Phillip Rodney Kwok
  • Publication number: 20250009256
    Abstract: A method of manufacturing a patient interface for sealed delivery of a flow of air at a continuously positive pressure with respect to ambient air pressure to an entrance to the patient's airways includes collecting anthropometric data of a patient's face. Anticipated considerations are identified from the collected anthropometric data during use of the patient interface. The collected anthropometric data is processed to provide a transformed data set based on the anticipated considerations, the transformed data set corresponding to at least one customised patient interface component. At least one patient interface component is modelled based on the transformed data set.
    Type: Application
    Filed: May 14, 2024
    Publication date: January 9, 2025
    Applicant: ResMed Pty Ltd
    Inventors: Tzu-Chin YU, Aaron Samuel DAVIDSON, Robert Henry FRATER, Benjamin Peter JOHNSTON, Paul Jan KLASEK, Robert Anthony PATERSON, Quangang YANG, Gerard Michael RUMMERY, Priyanshu GUPTA, Liam HOLLEY, Gordon Joseph MALOUF
  • Patent number: 12186240
    Abstract: The present invention provides an inpatient unit of modular design, built of recycled materials and environmentally friendly materials, allowing reconfiguration, redeployment and quick assembly, preventing indoor air from leaking, applicable to epidemic prevention and treating special patients, with high structural strength, lower cost and good environmental benefit.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: January 7, 2025
    Assignee: FU JEN CATHOLIC UNIVERSITY HOSPITAL, FU JEN CATHOLIC UNIVERSITY
    Inventors: Han-Sun Chiang, Ching-Chuan Jiang, Heng-Tai Chao, Wei-Lun Liu, Yi-Jen Jiang, Shiau-Jiun Lai, Heng-Lang Lin, Po-Jui Yu, Chin-Yu Hsieh, Chia-Jung Tsai, Yu-Hsuan Wu
  • Publication number: 20240408083
    Abstract: Ophthalmic formulations containing nintedanib, or a pharmaceutically acceptable salt thereof are provided. The ophthalmic formulations can contain microparticles or nanoparticles of nintedanib. Also provided are methods of using the ophthalmic formulations for treating ocular surface diseases, such as dry eye disease.
    Type: Application
    Filed: August 8, 2024
    Publication date: December 12, 2024
    Inventors: Tan NGUYEN, Chin-yu LAI
  • Patent number: 12161056
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: December 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chieh-Fei Chiu, Wen-Ting Chu, Yong-Shiuan Tsair, Yu-Wen Liao, Chin-Yu Mei, Po-Hao Tseng
  • Publication number: 20240383744
    Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Jhao-Yi Wang, Chin-Yu Ku, Wen-Hsiung Lu, Lung-Kai Mao, Ming-Da Cheng
  • Publication number: 20240369620
    Abstract: A method includes: positioning a wafer in a first probe chamber of a first probe apparatus by a robot arm, the first probe apparatus being adjacent a transfer rail, the robot arm, in operation, moving along the transfer rail; testing the wafer by the first probe apparatus; following the testing, transferring the wafer to an environmental buffer attached to the first probe chamber; cooling the wafer in the environmental buffer; and following the cooling, transferring the wafer from the environmental buffer to a second probe chamber of a second probe apparatus by the robot arm, the second probe apparatus being adjacent the transfer rail and offset from the first probe apparatus.
    Type: Application
    Filed: November 9, 2023
    Publication date: November 7, 2024
    Inventors: Jyu-Hua HSIAO, Chin-Yu LIN, Chien Fang HUANG, Kam Heng LEE, Jiun-Rong PAI