Patents by Inventor Chin Yu
Chin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071888Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.Type: ApplicationFiled: August 28, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
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Patent number: 11917472Abstract: Aspects directed towards Quality of Service (QoS) flow remapping are disclosed. In an example, upon detecting a mapping reconfiguration of a first QoS flow from a first data radio bearer (DRB) to another DRB, a Service Data Adaptation Protocol (SDAP) control protocol data unit (PDU) is generated indicating that a final SDAP data PDU associated with the first QoS flow has been transmitted on the first DRB. The SDAP control PDU is then transmitted via the first DRB. In another example, upon detecting a mapping reconfiguration of a first QoS flow from a first DRB to another DRB, an end marker parameter is set in an SDAP header of a first SDAP data PDU received from an upper layer after the mapping reconfiguration indicating that the first SDAP data PDU is a final SDAP data PDU associated with the first QoS flow transmitted on the first DRB.Type: GrantFiled: January 26, 2022Date of Patent: February 27, 2024Assignee: QUALCOMM IncorporatedInventors: Feilu Liu, Yu-Ting Yu, Srinivas Reddy Mudireddy, Tom Chin, Suli Zhao, Aziz Gholmieh, Xing Chen, Ozcan Ozturk, Arnaud Meylan
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Publication number: 20240061344Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.Type: ApplicationFiled: November 1, 2023Publication date: February 22, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsu-Ting HUANG, Tung-Chin WU, Shih-Hsiang LO, Chih-Ming LAI, Jue-Chin YU, Ru-Gun LIU, Chin-Hsiang LIN
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Patent number: 11908885Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The i magnetic element is wider than the isolation element. The semiconductor device structure further includes a conductive line over the isolation element.Type: GrantFiled: May 9, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Yu Ku, Chi-Cheng Chen, Hon-Lin Huang, Wei-Li Huang, Chun-Yi Wu, Chen-Shien Chen
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Publication number: 20240047397Abstract: A semiconductor device includes a substrate, one or more wiring layers disposed over the substrate, a passivation layer disposed over the one or more wiring layers, a first conductive layer disposed over the passivation layer, a second conductive layer disposed over the first conductive layer, an isolation structure formed in the first and second conductive layers to isolate a part of the first and second conductive layers, and a first metal pad disposed over the isolation structure and the part of the first and second conductive layers. In one or more of the foregoing or following embodiments, the semiconductor device further includes a second metal pad disposed over the second conductive layer and electrically isolated from the first metal pad.Type: ApplicationFiled: March 20, 2023Publication date: February 8, 2024Inventors: Bo-Yu CHIU, Pei-Wei LEE, Fu Wei LIU, Yun-Chung WU, Hao Chun YANG, Chin-Yu KU, Ming-Da CHENG, Ming-Ji LII
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Publication number: 20240047496Abstract: An image sensor includes a substrate, a grid, and a color filter. The grid is over the substrate. From a cross-sectional view, the grid includes a first grid and a second grid over the first grid, the first grid has lower portion that has a first sidewall and a second sidewall opposing the first sidewall, the second grid has a third sidewall and a fourth sidewall opposing the third sidewall, and a width between the third sidewall and the fourth sidewall is less than a width between the first sidewall and the second sidewall. The color filter extends through the grid structure.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Yu LIN, Keng-Ying LIAO, Su-Yu YEH, Po-Zen CHEN, Huai-Jen TUNG, Hsien-Li CHEN
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Publication number: 20240034619Abstract: A method includes forming an interconnect structure over a semiconductor substrate. The interconnect structure includes a plurality of dielectric layers, and the interconnect structure and the semiconductor substrate are in a wafer. A plurality of metal pads are formed over the interconnect structure. A plurality of through-holes are formed to penetrate through the wafer. The plurality of through-holes include top portions penetrating through the interconnect structure, and middle portions underlying and joining to the top portions. The middle portions are wider than respective ones of the top portions. A metal layer is formed to electrically connect to the plurality of metal pads. The metal layer extends into the top portions of the plurality of through-holes.Type: ApplicationFiled: January 9, 2023Publication date: February 1, 2024Inventors: Pei-Wei Lee, Fu Wei Liu, Szu-Hsien Lee, Yun-Chung Wu, Chin-Yu Ku, Ming-Da Cheng, Ming -Ji Lii
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Publication number: 20240033164Abstract: A compression garment for implementing circulatory-related disorder therapy includes a plurality of chambers. In some implementations, the compression garment further includes air supply tubes and tube guides for maintaining the air supply tubes on a predetermined pathway in or on the garment. In some implementations, the compression garment further includes three or more layers forming the macro-chambers and air supply channels for supplying air to the macro-chamber. In some implementations, the compression garment further includes a flexible foot chamber support assembly that allows bending around a periphery of a user's foot. In some implementations, the compression garment further includes chamber valves and a main air supply valve pneumatically connected to a central air supply line and configured to control the supply of pressurized air to at least two of the chamber valves.Type: ApplicationFiled: January 14, 2022Publication date: February 1, 2024Inventors: Dinesh Ramanan, Matthew Backler, Gaetano Caldarola, Charles Andrew William Hartson, Luke Klinkenberg, Blythe Rees-Jones, Francis Eric Saunders, Tzu-Chin Yu
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Publication number: 20240020243Abstract: In an example in accordance with the present disclosure, a method is described. According to the method, boundary values for a setting for a signal between a compute device and a peripheral device are determined. A target value for the setting is determined. The target value is a value between determined boundary values. The setting for the signal is adjusted to match the target value.Type: ApplicationFiled: April 29, 2020Publication date: January 18, 2024Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Cheng-Yan Chiang, James L. Mondshine, Charles Shaver, Khoa Huynh, Jia-Hung Lai, Bing-Hao Cheng, Kuang-Che Teng, Chin-Yu Wang
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Publication number: 20240017988Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.Type: ApplicationFiled: August 6, 2023Publication date: January 18, 2024Inventors: Jhao-Yi Wang, Chin-Yu Ku, Wen-Hsiung Lu, Lung-Kai Mao, Ming-Da Cheng
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SHOE UPPER DESIGN MODEL GENERATING METHOD, SYSTEM AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIA
Publication number: 20240020438Abstract: This invention provides a shoe upper design model generating method, system and non-transitory computer readable storage media, including steps of providing a 2D mapping boundary, providing a 3D upper, performing a flattening algorithm on the 3D upper with respect to the 2D mapping boundary, constructing a 2D upper boundary, creating an upper design drawing on the 2D upper boundary, intersecting the 2D upper boundary and the 2D mapping boundary to form a 2D upper design area and mapping grids in the 2D upper design area onto grids in the 3D upper, thereby obtaining an upper design model containing the mapping relation between the 2D upper design area and the 3D upper. Accordingly, the upper pattern making time and cost can be saved, and the distortion and deformation in the process of 2D-3D conversion can be reduced, thus the completed 2D upper design drawing can be used in production process directly.Type: ApplicationFiled: April 20, 2023Publication date: January 18, 2024Inventors: Wei-Hsiang TSAI, CHIN-YU CHEN, CHUN-HENG LIN, CHIH-PENG CHEN, FONG-YI SYU -
Publication number: 20240018994Abstract: A hinge device includes a fixed shaft, a rotating sleeve, a fixed connection member, a torsion spring, a rotating connection member and a friction resistance assembly. The rotating sleeve is rotatably mounted on the fixed shaft and is located between a fixed end and a free end. One end of the fixed connection member is fixedly connected to the free end, and the other end is provided with a first slot. Two ends of the torsion spring are respectively equipped with a first snap-in pin and a second snap-in pin. The first snap-in pin inserts into the first slot. An extension part protrudes from a fixed part of the of the rotating connection member and is provided with a second slot. The second snap-in pin inserts into the second slot. The friction resistance assembly is disposed on the fixed shaft to provide torsional resistance to the rotating sleeve.Type: ApplicationFiled: October 27, 2022Publication date: January 18, 2024Inventors: Chin-Yu Hsiao, Huan-Yu Huang
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Publication number: 20240014105Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes at least one substrate and an interconnection structure. The at least one substrate has a cavity partially defined by an inner sidewall of the at least one substrate and a channel disposed at a bottom of the at least one substrate. The channel laterally penetrates through the at least one substrate. The interconnections structure is disposed over the substrate, and the interconnection structure has a through hole penetrating through the interconnection structure. The through hole, the cavity and the channel are in spatial communication with each other.Type: ApplicationFiled: September 22, 2023Publication date: January 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Sheng Lin, Cheng-Lung Yang, Chin-Yu Ku, Ming-Da Cheng, Wen-Hsiung Lu, Tang-Wei Huang, Fu Wei Liu
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Publication number: 20240009067Abstract: A compression garment for circulatory-related disorder therapy includes a skin contacting layer, a second layer coupled to the skin contacting layer, and connectors disposed on the second layer. The skin contacting layer and the second layer form one or more macro-chambers. Each macro-chamber is partitioned into a plurality of micro-chambers. Each of the micro-chambers is in direct fluid communication with at least one other of the micro-chambers. Each of the connectors is configured to supply pressurized air directly into at least a corresponding one of the macro-chambers such that the pressurized air is delivered to at least one of the micro-chambers within the macro-chamber. The coupling of the skin contacting layer and the second layer is along a layer attachment profile that defines the macro-chambers and the micro-chambers. At least one of the micro-chambers is linked to another of the micro-chambers by way of a plurality of openings.Type: ApplicationFiled: April 15, 2021Publication date: January 11, 2024Inventors: Dinesh Ramanan, Blythe Guy Rees-Jones, Tzu-Chin Yu, Matthew John Backler, Francis Eric Saunders
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Patent number: 11862886Abstract: A connector clip is disclosed. The connector clip includes a base, a cover, a hinge coupling the cover and the base, and a fastener. The base has a first base side joined to a second base side via a connecting base side. The cover has a first cover side joined to a second cover side via a connecting cover side. The fastener holds the first base side and the first cover side in a fixed position when the connector clip is in a closed configuration in which the connecting base side is parallel to the connecting cover side. An internal cable opening is formed in part by the connecting base side and the connecting cover side when the connector clip is in the closed configuration. The connector clip secures a cable passing through the internal cable opening and connected to a board in its place in the closed configuration.Type: GrantFiled: February 23, 2022Date of Patent: January 2, 2024Assignee: QUANTA COMPUTER INC.Inventors: Yaw-Tzorng Tsorng, Chen-Chien Kuo, Tang-Shun-Lee Chen, Chin-Yu Lin
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Patent number: 11855007Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs are in the semiconductor device. Each of the TSVs has a first surface and a second surface opposite to the first surface. The first seal ring is located in proximity to an edge of the semiconductor structure and is physically connected to the first surface of each of the TSVs. The second seal ring is physically connected to the second surface of each of the TSVs.Type: GrantFiled: April 27, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
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Publication number: 20230405368Abstract: A personal entertainment respiratory apparatus provides air to a user to provide a fully immersive entertainment experience. The personal entertainment system may comprise a flow generator for providing the flow of air. A personal spatial respiratory interface may be coupled to the flow generator. The personal spatial respiratory interface may comprise an outlet for the flow generator. The personal spatial respiratory interface may further be configured to direct the flow of air within an ambient breathing proximity of a user. The personal entertainment respiratory apparatus may further comprise a controller and a sensory particle dispenser. The controller and sensory particle dispenser may be configured to selectively activate release of a sensory particle from the dispenser into the directed flow of air in response to an entertainment triggering signal.Type: ApplicationFiled: May 11, 2023Publication date: December 21, 2023Applicant: ResMed Pty LtdInventors: Tzu-Chin YU, Emma Anne Connell, David Creusot, Donald Darkin, Barton John Kenyon, Paul Jan Klasek, Andrew Sims, Quangang Yang, Phillip Rodney Kwok
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Patent number: 11848071Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: GrantFiled: December 8, 2021Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Patent number: 11841619Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.Type: GrantFiled: August 16, 2021Date of Patent: December 12, 2023Assignee: TAIWAN SEMINCONDUTOR MANUFACTURING COMPANY, LTD.Inventors: Hsu-Ting Huang, Tung-Chin Wu, Shih-Hsiang Lo, Chih-Ming Lai, Jue-Chin Yu, Ru-Gun Liu, Chin-Hsiang Lin
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Patent number: 11844184Abstract: An information processing system includes a housing, a circuit board in the housing, a functional module in the housing, and a module fixing device in the housing. The functional module is inserted into the circuit board. The module fixing device is connected to the functional module and is connected to the circuit board. The module fixing device comprises a clamping member and an elastic member. The clamping member is movably connected to the circuit board in a first direction and a second direction opposite to the first direction, the clamping member comprises a first clamping portion to clamp the functional module. The elastic member is connected to the clamping member, the elastic member is deformable in the first direction to drive the clamping member to move in the first direction to clamp the functional module.Type: GrantFiled: July 14, 2022Date of Patent: December 12, 2023Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.Inventors: Tung-Ho Shih, Hung-Wei Chen, Kuan-Chin Yu, Ming-Heng Lu