Patents by Inventor Ching-An Chung

Ching-An Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190363126
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 28, 2019
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Publication number: 20190361627
    Abstract: A control method of a memory device may include: (a) reading a read request of a host; (b) determining, by the processor, whether a logical address corresponding to the read request of the host is present in a cache; and (c) generating, by the processor, a data read command according the read request when the determination result of (b) indicates that the logical address corresponding to the read request is present in the cache, and transferring, by the processor, the data read command to one of the plurality of memory channels which corresponds to the physical address, in order to process the data read command.
    Type: Application
    Filed: March 19, 2019
    Publication date: November 28, 2019
    Inventors: Ching-Chung LAI, Lian-Chun LEE
  • Patent number: 10489620
    Abstract: A system and apparatus for assessing whether a personnel has complied with sanitation protocols. The system may incorporate wearable tags on each personnel which can communicate with a mesh network to confirm presence of the personnel. In an embodiment, a soap dispenser may be part of the mesh network such that, when the dispenser is activated, a personnel's presence is detected and recorded.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: November 26, 2019
    Assignee: WiSilica Inc.
    Inventors: Dennis Ching Chung Kwan, Suresh Kumar Singamsetty
  • Patent number: 10491416
    Abstract: This disclosure provides a system of intelligent lights together with control devices and sensors communicating over a wireless network, with methods to allow the lights to take actions based on logical combinations of events generated by other devices. The lights can function autonomously as they have built-in functions of logic processing, storage and wireless communications which allow them to receive events and take actions according to the stored logic configuration data. Complete freedom in the grouping of lights as well as association of control devices and sensors to each individual lights is enabled by this system architecture. Seamless communication coverage is enabled by a wireless protocol that allows the light to form a mesh network.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: November 26, 2019
    Assignee: WiSilica Inc.
    Inventors: Suresh Kumar Singamsetty, Dennis Ching Chung Kwan
  • Patent number: 10492280
    Abstract: A system integrates a wireless controller into a linear, alternating current-only driver. The system utilizes a light emitting diode driver to maintain a constant current to a light emitting diode when a current controller is operated by a pulse width modulated signal. The pulse width modulated signal to one or more light emitting diode circuits may be modified to reduce flicker, color mix, and temperature tune.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: November 26, 2019
    Assignee: WiSilica Inc.
    Inventors: Dennis Ching Chung Kwan, Suresh Kumar Singamsetty, Francis Antony
  • Patent number: 10475877
    Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
  • Publication number: 20190341524
    Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region, wherein the active region comprises multiple alternating well layers and barrier layers, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies at a distance of between 15 nm and 60 nm from the upper surface of the active region.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 7, 2019
    Inventors: Chia-Ming LIU, Chang-Hua HSIEH, Yung-Chung PAN, Chang-Yu TSAI, Ching-Chung HU, Ming-Pao CHEN, Chi SHEN, Wei-Chieh LIEN
  • Patent number: 10455048
    Abstract: A method for storing large amounts of data on a wireless device, said method comprising the steps of placing a wireless device on a wireless transmission unit; initializing the wireless device for transmission of data; authenticating the wireless device with an associated account or profile; verifying the storage capacity of the wireless device; determining what wireless standard is implemented by the device; and transmitting data to the wireless device; whereby the transmitted information may be later viewed and or accessed locally from the wireless device.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: October 22, 2019
    Assignee: WISILICA INC.
    Inventors: Suresh Kumar Singamsetty, Dennis Ching Chung Kwan
  • Publication number: 20190287860
    Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu
  • Publication number: 20190288027
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate and an image sensing element disposed within the substrate. The substrate has sidewalls defining a plurality of protrusions over the image sensing element. A first one of the plurality of protrusions including a first sidewall having a first segment. A line that extends along the first segment intersects a second sidewall of the first one of the plurality of protrusions that opposes the first sidewall.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 19, 2019
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Jiech-Fun Lu, Shih-Pei Chou
  • Patent number: 10419889
    Abstract: A system for providing location awareness in a building automation system includes a mesh network of lighting devices on a first floor of a building and a second mesh network of lighting devices on a second floor of the building each aggregating a tracking tag signals at a floor level gateway of the building automation system.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: September 17, 2019
    Assignee: WiSilica Inc.
    Inventors: Suresh Singamsetty, Dennis Ching Chung Kwan, Francis Antony
  • Patent number: 10411458
    Abstract: An overvoltage protection device including an output stage, a first switch and a first load providing circuit is provided. The output stage has a first input terminal to receive a first signal, and generates an output signal at an output terminal of the output stage according to the first signal. A first terminal of the first switch is coupled to the first input terminal of the output stage, and a control terminal of the first switch receives a second signal. The first signal is the delayed second signal. The first load providing circuit is coupled to a second terminal of the first switch. The first load providing circuit provides an impedance to the first input terminal when the first switch is turned on.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 10, 2019
    Assignee: ALi Corporation
    Inventors: Ching-Chung Cheng, Kuo-Kai Lin
  • Publication number: 20190252241
    Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Ching-Chung SU, Jiech-Fun LU, Jian WU, Che-Hsiang HSUEH, Ming-Chi WU, Chi-Yuan WEN, Chun-Chieh FANG, Yu-Lung YEH
  • Publication number: 20190252317
    Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 15, 2019
    Inventors: CHEN-FA LU, CHENG-YUAN TSAI, CHING-CHUNG HSU, CHUNG-LONG CHANG
  • Patent number: 10373872
    Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 6, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu
  • Publication number: 20190236021
    Abstract: A memory access method for selectively creating a simplified mapping table includes the steps of: selecting one of a plurality of partitions of an original mapping table so as to use one physical page address in a selected partition as a start physical page address; scanning each entry of the selected partition so as to search a randomly mapped entry in the selected partition; determining whether a memory space required for creating the simplified mapping table is smaller than a memory space required for the selected partition; and selectively storing the start physical page address, the number of the randomly mapped entries, and a logical page address and a physical page address recorded on each randomly mapped entry according to the determination result of the determining step so as to create a simplified mapping table.
    Type: Application
    Filed: December 4, 2018
    Publication date: August 1, 2019
    Inventors: Ching-Chung LAI, Lian-Chun LEE
  • Patent number: 10361234
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10349366
    Abstract: An activity monitoring system comprising a plurality of wireless units wherein a first wireless unit comprises a wireless transceiver to broadcast at least one timing signal; a second wireless unit comprises: a wireless transceiver to receive at least one signal; a monitoring device that generates monitoring data; a memory to store the monitoring data; a processor to synchronize a time with the corresponding monitoring data; and wherein the second wireless unit: processes the received timing signal from the first wireless unit; synchronizes the monitoring data with the timing signal resulting in a time-synchronized data stream.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 9, 2019
    Assignee: WISILICA INC.
    Inventors: Dennis Ching Chung Kwan, Suresh Kumar Singamsetty
  • Patent number: 10333367
    Abstract: A planar energy conversion device with a plurality of micro-conversion units is provided and includes a carrier. The carrier includes a plurality of cavities arranged horizontally. The cavities correspond in position to the micro-conversion units, respectively. Each micro-conversion unit includes: a magnetic rotor disposed in the corresponding cavity; and at least one ring-shaped stator surrounding the magnetic rotor, the magnetic rotor being integrated into the carrier and including a magnet component and a winding unit. The magnet component has multiple protruding portions horizontally arranged along the edge of the corresponding cavity. The winding unit has multiple winding elements corresponding in position to the protruding portions, respectively.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 25, 2019
    Assignee: SPEEDY CIRCUITS CO., LTD.
    Inventor: Ching Chung Lien
  • Patent number: 10323331
    Abstract: The present disclosure provides a valuable metal selectively adsorbing electrode, including: an electrode formed by a carbon-containing material; and a protein of a bacterium of genus Tepidimonas immobilized on the electrode formed by a carbon-containing material to form the valuable metal selectively adsorbing electrode, wherein the valuable metal includes gold, palladium, silver or indium.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 18, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Li-Ching Chung, Chia-Heng Yen, Teh-Ming Liang, Ren-Yang Horng, Min-Chao Chang, Hsin Shao, Po-I Liu, Chih-Hsiang Fang, Yin-Lung Han, Kai-Chun Fan