Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

Abstract: Various embodiments of the present disclosure are directed towards a method for manufacturing a semiconductor structure. The method includes forming photodetectors within a semiconductor substrate. A charge release layer is deposited over the semiconductor substrate. A conductive contact is formed over the charge release layer such that a contact protrusion of the conductive contact extends through the charge release layer. The charge release layer is disposed along opposing sidewalls of the conductive contact. The charge release layer is electrically coupled to ground via the conductive contact.

Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.

Abstract: A holder includes a substrate, at least one first fastener and a pressure block. The substrate includes a top surface, a primary recess recessed from the top surface, at least one first side-recess recessed from the top surface, wherein the first side-recess neighbors and communicates with the primary recess, and a channel recess recessed from the top surface, wherein the channel recess neighbors and communicates with the primary recess, and the first side-recess and the channel recess are positioned at opposite sides of the primary recess. The first fastener is disposed in the first side-recess, wherein the first fastener has a top substantially leveled with the top surface of the substrate. The pressure block is disposed in the channel recess, wherein the pressure block has a top substantially leveled with the top surface of the substrate.

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. The substrate has a plurality of protrusions disposed along a first side of the substrate over the image sensing element and a ridge disposed along the first side of the substrate. The ridge continuously extends around the plurality of protrusions.

Abstract: A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.

Abstract: The present disclosure describes the formation of a pad structure in an image sensor device using a sacrificial isolation region and a silicon oxide based stack with no intervening nitride etch-stop layers. The image sensor device includes a semiconductor layer comprising a first horizontal surface opposite to a second horizontal surface; a metallization layer formed on the second horizontal surface of the semiconductor layer, where the metallization layer includes a dielectric layer. The image sensor device also includes a pad region traversing through the semiconductor layer from the first horizontal surface to the second horizontal surface. The pad region includes an oxide layer with no intervening nitride layers formed on the dielectric layer of the metallization layer and a pad structure in physical contact with a conductive structure of the metallization layer.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a charge release layer. A photodetector is disposed within a semiconductor substrate. An etch stop layer overlies the photodetector. A color filter overlies the etch stop layer. A dielectric grid structure surrounds the color filter. The charge release layer is sandwiched between the dielectric grid structure and the etch stop layer. The charge release layer surrounds the color filter and comprises a conductive material. The charge release layer directly contacts the color filter.

Abstract: A backlight module and a display device are provided. The backlight module includes a light source structure and at least one optical film. The optical film is disposed above the light source structure. The optical film includes a main body and plural optical structures. The optical structures are disposed on the main body. Each of the optical structures is a tapered structure. Each of the optical structures has plural side surfaces, and a portion of light emitted from the light source structure is guided toward plural primary directions when passing through the side surfaces of the optical structures, and therefore the light emitted from the light source is no longer concentrated on the top of each of the optical structures.

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region.

Abstract: A light guide plate, a backlight module and a display device are provided. The light guide plate includes a main body and plural prism portions. The main body has a first extending direction and a second extending direction. The main body includes a light-incident surface extending along the first extending direction and an optical surface connected to the light-incident surface. The optical surface has a first region, a second region and a third region which are arranged along the second extending direction. The prism portions are disposed on the optical surface and extend along the second extending direction. An occupied area ratio of the prism portions located in the first region is greater than an occupied area ratio of the prism portions located in the second region and is smaller than an occupied area ratio of the prism portions located in the third region.

Abstract: A robotic system includes a base and at least one axis actuation module. The base includes an input power conversion device. A power input terminal of the input power conversion device receives an input voltage. The input voltage is converted into a first voltage by the input power conversion device. The first voltage is outputted from a power output terminal of the input power conversion device. The at least one axis actuation module is installed on the base. Each axis actuation module includes a motor, an axis power conversion device and a driving device. The first voltage is converted into a second voltage with a rated voltage value by the axis power conversion device. The second voltage is converted into a third voltage by the driving device. The third voltage is provided to the motor.

Abstract: Provided are a hybrid distributed file system architecture structure, an applied file storage processing method, a dynamic migration method, and application thereof. The file storage processing method comprises: acquiring storage attributes of a file to be stored, wherein the storage attributes at least include a size of the file; determining, according to a pre-configured storage rule and the attributes of the file to be stored, in which distributed file system the file to be stored is stored; and storing the file to be stored in the determined distributed file system. The method further comprises migrating, according to a predetermined policy, a file that has been stored in a predetermined storage location. The device intelligently selects a file underlying storage policy according to file feature attributes to decide whether to migrate the file and to which file system the file is migrated so as to satisfy usage equalization of different file systems and also minimize performance degradation.

Abstract: A control method of a storage device may include the steps of determining, by a storage device controller of the storage device, whether the storage device has to move internal data; deciding, by the storage device controller, a data movement allocation ratio based on at least some of internal data movement requests and the number of free pages in the storage device, when it is determined that the storage device has to move internal data; and allocating, by the storage device controller, one or more programming times to complete a first data number of internal data movement operations corresponding to at least some of the internal data movement requests and a second data number of host data write operations, such that the ratio of the first and second data numbers coincides with the data movement allocation ratio.

Abstract: The present disclosure, in some embodiments, relates to method of forming an integrated chip. The method may be performed by forming an image sensing element within a substrate. A dry etching process is performed on the substrate to form a plurality of intermediate protrusions defined by the substrate. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions from the plurality of intermediate protrusions.

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

Abstract: Provided is a lens driver movable in a direction parallel to an optical axis, arranged on a lens driver movable in a plane orthogonal to the optical axis, and accommodated in a casing. The lens driver includes: a fixture base, a support frame A, a lens module, a spring piece, a first driving coil, a magnet and a yoke. The lens driver includes: a base; a connection terminal and a conductive member A arranged on the base; a support frame B supported by a support part; a conductive member B arranged on the support frame; a center holding part for keeping the base and the support frame B at a center of the optical axis; a second driving coil arranged on the base; and a magnetic detecting element. The lens driver provided can achieve purposes of anti-image dithering and simplifying assembly to obtain good image quality.