Patents by Inventor Ching-An Chung

Ching-An Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200311035
    Abstract: Provided are a hybrid distributed file system architecture structure, an applied file storage processing method, a dynamic migration method, and application thereof. The file storage processing method comprises: acquiring storage attributes of a file to be stored, wherein the storage attributes at least include a size of the file; determining, according to a pre-configured storage rule and the attributes of the file to be stored, in which distributed file system the file to be stored is stored; and storing the file to be stored in the determined distributed file system. The method further comprises migrating, according to a predetermined policy, a file that has been stored in a predetermined storage location. The device intelligently selects a file underlying storage policy according to file feature attributes to decide whether to migrate the file and to which file system the file is migrated so as to satisfy usage equalization of different file systems and also minimize performance degradation.
    Type: Application
    Filed: March 27, 2020
    Publication date: October 1, 2020
    Inventors: Yeh-Ching CHUNG, Lidong ZHANG, Yongwei Wu
  • Patent number: 10785672
    Abstract: In some configurations, the method of operating a system with dynamic wireless network topology with reduced spectrum flooding involve scanning with a first device in mesh network for beacon packets from other devices in the mesh network during a random back off period. In response to the first device not receiving a beacon packet from the other devices during the random back off period, the first device initiates an election protocol by sending an election protocol packet with its unique election protocol identifier to the other devices. In response to receiving a beacon packet from a second device, the first device stores the unique node identifier, assigns the second device as a leader node device, retransmits the unique node identifier of the second device and leader node information in a protocol packet. A command packet is communicated through the mesh network by way of at least one leader node device.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 22, 2020
    Assignee: WiSilica Inc.
    Inventors: Dennis Ching Chung Kwan, Suresh Kumar Singamsetty
  • Patent number: 10784150
    Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Chung Su, Jiech-Fun Lu, Jian Wu, Che-Hsiang Hsueh, Ming-Chi Wu, Chi-Yuan Wen, Chun-Chieh Fang, Yu-Lung Yeh
  • Publication number: 20200296503
    Abstract: A speaker device includes an external housing, a sound guide structure, and a speaker unit. The sound guide structure is located in the external housing and has a paraboloid. The speaker unit is located in the external housing and configured to sound towards the paraboloid. The paraboloid has a focus. The speaker unit has a sound emitting surface. The center of the sound emitting surface is substantially coincident with the focus.
    Type: Application
    Filed: August 20, 2019
    Publication date: September 17, 2020
    Inventors: Chih-Hsiang HSU, Ching-Chung CHEN
  • Patent number: 10776372
    Abstract: The present disclosure provides a method for computing a support of an itemset candidate based on graph structure data, a method for determining a frequent itemset using the same, and a method for determining a frequent itemset based on a prefix tree. The method for computing a support of an itemset candidate based on graph structure data comprises: converting data in a database to graph structure data (S101); obtaining an itemset candidate from the database (S102); obtaining a connected component corresponding to the itemset candidate in the graph structure data (S103); determining the number of vertices included in the connected component (S104); and determining the number of vertices as the support of the itemset candidate (S105).
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: September 15, 2020
    Assignee: Research Institute of Tsinghua University in Shenzhen
    Inventors: Yeh-Ching Chung, Rui Zhang, Wenguang Chen
  • Publication number: 20200286981
    Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
  • Patent number: 10754786
    Abstract: A memory access method for selectively creating a simplified mapping table includes the steps of: selecting one of a plurality of partitions of an original mapping table so as to use one physical page address in a selected partition as a start physical page address; scanning each entry of the selected partition so as to search a randomly mapped entry in the selected partition; determining whether a memory space required for creating the simplified mapping table is smaller than a memory space required for the selected partition; and selectively storing the start physical page address, the number of the randomly mapped entries, and a logical page address and a physical page address recorded on each randomly mapped entry according to the determination result of the determining step so as to create a simplified mapping table.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventors: Ching-Chung Lai, Lian-Chun Lee
  • Patent number: 10750518
    Abstract: An antenna system includes: a plurality of antennas; a switching unit, having a plurality of switches, wherein each of the plurality of switches and the corresponding antenna are in a conducting state or in a non-conducting state; a communication unit, connected with each of the plurality of switches of the switching unit, and coupled with the antennas, wherein the communication unit receives a reference value group of the corresponding antenna from the switch in the conducting state; and a control unit, connected with the switching unit and the communication unit, wherein the control unit receives the reference value group from the communication unit, and compares the reference value group with an threshold, to determine whether the reference value group conforms to a pre-determined condition or not, and outputs a restarting instruction to restart the switching unit when the reference value group does not satisfy the pre-determined condition.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: August 18, 2020
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Zih-Guang Liao, Wen-Hsin Lin, Ching-Chung Tang, Tsung-Hsun Hsieh, You-Fu Cheng
  • Patent number: 10736177
    Abstract: In some configurations, the method of operating a system with dynamic wireless network topology with reduced spectrum flooding involve scanning with a first device in mesh network for beacon packets from other devices in the mesh network during a random back off period. In response to the first device not receiving a beacon packet from the other devices during the random back off period, the first device initiates an election protocol by sending an election protocol packet with its unique election protocol identifier to the other devices. In response to receiving a beacon packet from a second device, the first device stores the unique node identifier, assigns the second device as a leader node device, retransmits the unique node identifier of the second device and leader node information in a protocol packet. A command packet is communicated through the mesh network by way of at least one leader node device.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 4, 2020
    Assignee: WiSilica Inc.
    Inventors: Dennis Ching Chung Kwan, Suresh Kumar Singamsetty, Francis Antony
  • Publication number: 20200233611
    Abstract: A control method of a storage device wherein a host cannot transfer a command to the storage device when the storage device transfers data to the host, after which there is a data transfer delay time period and no data is transferred to the host until a read command is received from the host, the control method comprising the steps of: detecting, by a memory controller of the storage device, a host delay time of the host each time a read command is received from the host during the data transfer delay time period; and adjusting, by the memory controller, the data transfer delay time period based on one or more of the detected host delay times.
    Type: Application
    Filed: October 21, 2019
    Publication date: July 23, 2020
    Inventors: Chun-Shu CHEN, Lian-Chun LEE, Ching-Chung LAI
  • Publication number: 20200225403
    Abstract: A light guide plate includes a main body, stripe structures, and light-adjusting structures. The main body includes a light-incident surface and an optical surface. The stripe structures are disposed on the optical surface. The light-adjusting structures are disposed between two adjacent stripe structures. Each of the light-adjusting structures includes a first light active surface and a second light active surface. The first light active surface faces towards the light-incident surface. The second light active surface faces towards an opposite light-incident surface. The first light active surface and the second light active surface are inclined towards different directions and formed a non-symmetrical shape. A first included angle is formed between the first light active surface and the optical surface. A second included angle is formed between the second light active surface and the optical surface. The first included angle and the second included angle are acute angles.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Inventors: Chia-Yin Chang, Chin-Ting Weng, Hao Chen, Yi-Ching Chung
  • Patent number: 10714576
    Abstract: A device includes an epitaxy structure having a recess therein, a dielectric layer over the epitaxy structure, the dielectric layer having a contact hole communicating with the recess, a dielectric spacer liner (DSL) layer on a sidewall of the recess, a barrier layer on the DSL layer, and a conductor. The DSL layer has an opening. The DSL layer extends further into the epitaxy structure than the barrier layer. The conductor is disposed in the contact hole and electrically connected to the epitaxy feature through the opening of the DSL layer.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Cheng Hung, Kei-Wei Chen, Yu-Sheng Wang, Ming-Ching Chung, Chia-Yang Wu
  • Publication number: 20200212201
    Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 2, 2020
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Ping-Hung Chiang
  • Publication number: 20200182926
    Abstract: A holder includes a substrate, at least one first fastener and a pressure block. The substrate includes a top surface, a primary recess recessed from the top surface, at least one first side-recess recessed from the top surface, wherein the first side-recess neighbors and communicates with the primary recess, and a channel recess recessed from the top surface, wherein the channel recess neighbors and communicates with the primary recess, and the first side-recess and the channel recess are positioned at opposite sides of the primary recess. The first fastener is disposed in the first side-recess, wherein the first fastener has a top substantially leveled with the top surface of the substrate. The pressure block is disposed in the channel recess, wherein the pressure block has a top substantially leveled with the top surface of the substrate.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 11, 2020
    Inventors: Ching-Chung WANG, Jui-Hsiu JAO
  • Publication number: 20200176726
    Abstract: The invention provides a flexible battery comprising a flexible battery unit, at least one protective layer formed by a flexible material, and an enclosure defining an interior space. The at least one protective layer is formed on one side of the battery unit to define a stack structure which is placed hermetically inside the interior space of the enclosure. The at least one protective layer is configured to give a uniform curvature in a bending direction along which the battery is bent. The at least one protective layer is arranged in such a way to shield the battery unit from impacts of the enclosure caused by deformation and/or bending of the battery.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 4, 2020
    Inventors: Ching Chung POON, Man Yung David YEUNG
  • Patent number: 10672860
    Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung Hsu, Chung-Long Chang, Tsung-Yu Yang, Hung-Chi Li, Cheng-Chieh Hsieh, Che-Yung Lin, Grace Chang
  • Publication number: 20200141012
    Abstract: A multi-tank hydrogen-oxygen separation reactor is provided, including at least two hydrogen-oxygen separation reactors, and each of the hydrogen-oxygen separation reactors including an outer tank, an inner tank, a plurality of connection holes, an electrolytic solution, a first support portion, a first electrode, a first vent pipe, a second support portion, a second electrode, and a second vent pipe. The multi-tank hydrogen-oxygen separation reactor is able to enhance the efficiency of electrolyzing hydrogen and oxygen effectively and avoid explosion when hydrogen and oxygen coexist.
    Type: Application
    Filed: November 5, 2019
    Publication date: May 7, 2020
    Inventor: Ching-Chung Tsai
  • Publication number: 20200141781
    Abstract: A volume meter auxiliary module is configured to be assembled on a fluid volume meter. The volume meter auxiliary module includes a first assembly member and a second assembly member. The first assembly member includes a clamping structure configured to fix the first assembly member on the fluid volume meter. The second assembly member is configured to connect with the first assembly member. The second assembly member includes a casing body, a light emitter, an image-capturing piece and a cover. The casing body has a first opening and a second opening. The first opening is located at a bottom of the casing body. The light emitter is disposed inside the casing body. The image-capturing piece is disposed inside the casing body. The cover connects with the casing body and covers the second opening. The cover is rotatable relative to the casing body.
    Type: Application
    Filed: October 18, 2019
    Publication date: May 7, 2020
    Inventor: Ching-Chung CHEN
  • Publication number: 20200126976
    Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Yu CHEN, Chih-Ping CHAO, Chun-Hung CHEN, Chung-Long CHANG, Kuan-Chi TSAI, Wei-Kung TSAI, Hsiang-Chi CHEN, Ching-Chung HSU, Cheng-Chang HSU, Yi-Sin WANG
  • Publication number: 20200125562
    Abstract: The present disclosure provides a method for computing a support of an itemset candidate based on graph structure data, a method for determining a frequent itemset using the same, and a method for determining a frequent itemset based on a prefix tree. The method for computing a support of an itemset candidate based on graph structure data comprises: converting data in a database to graph structure data (S101); obtaining an itemset candidate from the database (S102); obtaining a connected component corresponding to the itemset candidate in the graph structure data (S103); determining the number of vertices included in the connected component (S104); and determining the number of vertices as the support of the itemset candidate (S105).
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Yeh-Ching CHUNG, Rui ZHANG, Wenguang CHEN