Patents by Inventor Ching-An Huang

Ching-An Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240080180
    Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.
    Type: Application
    Filed: December 20, 2022
    Publication date: March 7, 2024
    Inventors: Chih-Fan HSU, Wei-Chao CHEN, Jing-Lun Huang, Ming-Ching Chang, Feng-Hao Liu
  • Patent number: 11925002
    Abstract: A casing structure with functionality of effective thermal management is disclosed, which consists of a casing member, a low thermal conductivity medium, a second heat spreader, and a first heat spreader. When a user operates the electronic device, heat generated from CPU and/or GPU is transferred to the second heat spreader via the first heat spreader, and then is two-dimensionally spread in the second heat spreader. Consequently, the heat is dissipated away from the casing member to air due to the outstanding thermal radiation ability of the casing member. The low thermal conductivity medium is adopted for controlling a heat transfer of heat transferring paths from the heat source and ends to the casing member. By applying the casing structure in an electronic device by a form of a top casing and/or a back casing, an outer surface temperature of the casing member can be well controlled.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: March 5, 2024
    Assignee: AMLI MATERIALS TECHNOLOGY CO., LTD.
    Inventors: Jian-Jia Huang, Chun-Kai Lin, Chih-Ching Chen
  • Patent number: 11923413
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Publication number: 20240071849
    Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Jian-You Chen, Kuan-Yu Huang, Li-Chung Kuo, Chen-Hsuan Tsai, Kung-Chen Yeh, Hsien-Ju Tsou, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20240071515
    Abstract: Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 29, 2024
    Inventors: Ching-Huang Lu, Vinh Quang Diep, Avinash Rajagiri, Yingda Dong
  • Publication number: 20240071530
    Abstract: A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. During a program verify operation of the program operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. A pass through read voltage level associated with the target wordline is identified. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline or a second wordline, wherein the pass through read voltage level is the read voltage level reduced by an offset value.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 29, 2024
    Inventors: Ching-Huang Lu, Hong-Yan Chen, Yingda Dong
  • Publication number: 20240062827
    Abstract: A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 22, 2024
    Inventors: Ronit Roneel Prakash, Pitamber Shukla, Ching-Huang Lu, Murong Lang, Zhenming Zhou
  • Publication number: 20240061608
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that a temperature associated with the memory device satisfies a threshold criterion; determining a memory access operation type of the memory access operation; and performing the memory access operation on the set of cells associated with the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the memory access operation type and the temperature associated with the memory device.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Inventors: Zhenming Zhou, Ching-Huang Lu, Murong Lang
  • Publication number: 20240061583
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Inventors: Zhenming Zhou, Ching-Huang Lu, Murong Lang
  • Patent number: 11905973
    Abstract: A fan assembly including a fan frame and an impeller. The fan frame includes a frame body and a first peripheral protruding plate and has an air inlet and an air outlet. The first peripheral protruding plate protrudes from a side of the frame body and forms an air channel together with the frame body. The first peripheral protruding plate is configured to reduce a noise made by the fan assembly. The air inlet is in fluid communication with the air outlet via the air channel. The impeller is rotatably disposed on the frame body and located in the air channel. The protruding height of the first peripheral protruding plate relative to the frame body ranges from 50 to 100 percent of an overall axial thickness of the impeller.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: February 20, 2024
    Assignees: MICRO-STAR INT'L CO., LTD., MSI COMPUTER (SHENZHEN) CO., LTD.
    Inventors: Yi Wen Chen, Yung Ching Huang, Shang-Chih Yang
  • Publication number: 20240057343
    Abstract: Provided are ferroelectric tunnel junction (FTJ) structures, memory devices, and methods for fabricating such structures and devices. An FTJ structure includes a first electrode, a ferroelectric material layer, and a catalytic metal layer in contact with the ferroelectric material layer.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuen-Yi Chen, Yu-Sheng Chen, Yi Ching Ong, Kuo-Ching Huang
  • Publication number: 20240055026
    Abstract: A storage drive assembly is provided. The storage drive assembly includes a storage drive sized and shaped for insertion into a slot within a chassis, a latching mechanism coupled to a first end of the storage drive, the latching mechanism including an actuation component actuable to transition the latching mechanism from a locked state in which the latching mechanism restricts displacement of the storage drive relative to the chassis to an unlocked state in which the latching mechanism enables displacement of the storage drive assembly relative to the chassis, and a drive secure cover plate adapted to removably mate with the latching mechanism in the locked state, the mated drive secure cover plate preventing physical access to the actuation component.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 15, 2024
    Inventors: Wu-Shu LIN, Fredrick Anthony CONSTANTINO, Kevin Jay LANGSTON, Chia-Ching HUANG
  • Publication number: 20240053896
    Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A sensing time is determined using the cycle number and the group. The command is executed using the sensing time.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 15, 2024
    Inventors: Yu-Chung Lien, Zhenming Zhou, Murong Lang, Ching-Huang Lu
  • Publication number: 20240053901
    Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A bitline voltage is determined using the cycle number and the group. The command is executed using the bitline voltage.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 15, 2024
    Inventors: Yu-Chung Lien, Ching-Huang Lu, Zhenming Zhou
  • Patent number: 11901010
    Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vinh Q. Diep, Ching-Huang Lu, Yingda Dong
  • Publication number: 20240045601
    Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Inventors: Yu-Chung LIEN, Ching-Huang LU, Zhenming ZHOU
  • Publication number: 20240047508
    Abstract: A semiconductor structure includes an inductive metal line located in a dielectric material layer that overlies a semiconductor substrate and laterally encloses a first area; and an array of first ferromagnetic plates including a first ferromagnetic material and overlying or underlying the inductive metal line. For any first point that is selected within volumes of the first ferromagnetic plates, a respective second point exists within a horizontal surface of the inductive metal line such that a line connecting the first point and the second point is vertical or has a respective first taper angle that is less than 20 degrees with respective to a vertical direction. The magnetic field passing through the first ferromagnetic plates is applied generally along a hard direction of magnetization and the hysteresis effect is minimized.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 8, 2024
    Inventors: Yu-Sheng Chen, Hsien Jung Chen, Kuen-Yi Chen, Chien Hung Liu, Yi Ching Ong, Yu-Jen Wang, Kuo-Ching Huang, Harry-Hak-Lay Chuang
  • Publication number: 20240046998
    Abstract: Apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. The set of memory components include a first memory block comprising first units of linearly arranged memory cells and a second memory block comprising second units of linearly arranged memory cells. The set of memory components include a slit portion dividing the first and second memory blocks. The slit portion includes a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Inventors: Yu-Chung Lien, Ching-Huang Lu, Zhenming Zhou
  • Patent number: D1016792
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: March 5, 2024
    Assignee: Acer Incorporated
    Inventors: Hsueh-Wei Chung, Pao-Ching Huang, Kai-Teng Cheng, Hung-Chi Chen
  • Patent number: D1016804
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: March 5, 2024
    Assignee: Acer Incorporated
    Inventors: Yun-Ju Chou, Pao-Ching Huang