Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A sensing time is determined using the cycle number and the group. The command is executed using the sensing time.

Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A bitline voltage is determined using the cycle number and the group. The command is executed using the bitline voltage.

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation.

Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Abstract: A semiconductor structure includes an inductive metal line located in a dielectric material layer that overlies a semiconductor substrate and laterally encloses a first area; and an array of first ferromagnetic plates including a first ferromagnetic material and overlying or underlying the inductive metal line. For any first point that is selected within volumes of the first ferromagnetic plates, a respective second point exists within a horizontal surface of the inductive metal line such that a line connecting the first point and the second point is vertical or has a respective first taper angle that is less than 20 degrees with respective to a vertical direction. The magnetic field passing through the first ferromagnetic plates is applied generally along a hard direction of magnetization and the hysteresis effect is minimized.

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. The set of memory components include a first memory block comprising first units of linearly arranged memory cells and a second memory block comprising second units of linearly arranged memory cells. The set of memory components include a slit portion dividing the first and second memory blocks. The slit portion includes a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells.

Abstract: A load switch circuit is provided. The load switch circuit includes a control chip and a current limit protection circuit. The control chip is operated at a power supply voltage, configured to receive an input voltage, and controlled by an enable signal to provide an output voltage and an output current to a load. The current limit protection circuit is configured to provide a current limit control voltage to a current limit and low power pin of the control chip, so that the control chip may adjust a current limit of the output current.

Abstract: A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.

Abstract: A memory device includes a transistor device; a memory cell electrically coupled to a source or drain of the transistor device, wherein the memory cell includes an FJT structure; and a heating structure formed around the memory cell on a plurality of sides. The FJT structure includes a first conductive electrode having sidewalls that extend in a vertical direction to a first elevation level, a second conductive electrode having sidewalls that extend in the vertical direction to the first elevation level, and a switching barrier disposed between the first conductive electrode and the second conductive electrode and having sidewalls that extend in the vertical direction to the first elevation level, wherein the vertically extending sidewalls of the first conductive electrode, the second conductive electrode, and the switching barrier terminate at the first elevation level. The switching barrier includes ferroelectric (Fe) material that may be polarized to store information.

Abstract: An antenna phase control method is applied to an antenna phase control device and an antenna, the antenna disposed on a moving carrier. The method includes obtaining a location information of the moving carrier; obtaining a destination information of the moving carrier and generating a navigation information according to the location information and the destination information; calculating at least one preset location point in the path and a phase information of the antenna corresponding to the at least one preset location point; and controlling a phase of the antenna according to the phase information when the moving carrier reaches the at least one preset location point. The present disclosure also provides an antenna phase control device.

Abstract: An antenna phase control method is applied to an antenna phase control device, the antenna disposed on a moving carrier to communicate with a satellite. The method includes obtaining an initial phase of the antenna, obtaining an instant rotation information of a steering wheel of the moving carrier and speed information of the moving carrier, calculating a compensation phase of the antenna according to the instant rotation information and the speed information, and adjusting the initial phase of the antenna according to the compensation phase. The present disclosure also provides an antenna phase control device. The present disclosure can calculate the antenna phase according to the direction information and the speed information of the moving carrier, so as to dynamically adjust the radiation direction of the antenna.

Abstract: A battery module including a battery frame, a plurality of locking structures, a plurality of battery units, and a plurality of lug structures is provided. The battery frame is provided with an accommodating space. The battery frame includes a first portion extending along a first direction and a second portion extending along a second direction. The first direction is different from the second direction. The locking structures are disposed on the battery frame. At least one of the plurality of locking structures is disposed on an outer side of each of the first portion and the second portion. The battery units are disposed in the accommodating space. Each of the lug structures includes a lock portion configured to detachably engage with one of the locking structures.

Abstract: A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.

Abstract: A lock assembly includes a casing, a blocking unit, and a lock unit. The blocking unit includes a blocking member operable to move between an open position and a block position. The lock unit includes an engaging member, an electric unlock module, and a manual unlock module. The engaging member has a main body having first and second abutment portions, and is movable between an engaging position for engaging the blocking member when the blocking member is in the block position, and an unlocked position for disengaging from the blocking member. One of the electric unlock module and the manual unlock module is operable to abut a push member thereof against a corresponding one of the first and second abutment portions to linearly move the engaging member.

Abstract: The invention comprises a light emitting diode chip and a package substrate. The light emitting diode chip is provided with a semiconductor epitaxial structure, a lateral extending interface structure, a chip conductive structure, an N-type electrode located above the semiconductor epitaxial structure and a P-type bypass detection electrode located on the lateral extending interface structure. The chip conductive structure is provided with a P-type main electrode located on a lower side. The package substrate comprises a plurality of electrode contacts through which the N-type electrode, the P-type bypass detection electrode and the P-type main electrode are connected, and a process quality of a alternative substrate adhesive layer in one of the semiconductor epitaxial structure and the chip conductive structure and a chip-substrate bonding adhesive layer between the P-type main electrode and the package substrate is evaluated by detecting electrical characteristics.

Abstract: A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.

Abstract: A modified electrode, manufacturing method thereof and use thereof are provided. The manufacturing method includes steps of soaking a copper substrate in a solution to obtain a BiOI/copper(I) iodide, BiOI/copper(I) iodide/metallic bismuth, and copper(I) iodide/metallic bismuth composite modified electrodes by electroless plating method. The obtained electrodes, designated as bismuth-based modified electrode, can be used for the electrohydrodimerization of acrylonitrile to synthesize adiponitrile.