Abstract: The disclosure describes an antenna that is formed from a continuous material according to some embodiments. In some embodiments, the antenna includes a plurality of individual antenna modules each formed from the continuous material. In some embodiments, each antenna module is configured to resonate at a plurality of frequencies. In some embodiments, each antenna module is configured to receive a voltage and/or current from a single feeder. In some embodiments, each of the antenna modules are effectively electrically isolated from each other. In some embodiments, each antenna module includes one or more driven portions and one or more parasitic portions. In some embodiments, the one or more driven portions are configured and/or arranged to induce a voltage in the one or more parasitic portions.

Abstract: A substrate assembly is provided, including a first substrate, an active element layer, a plurality of first electrodes, a circuit substrate, and a plurality of second electrodes. The active element layer is disposed on the first substrate. The plurality of first electrodes are disposed on the first substrate and arranged along a first direction. The circuit substrate is partially overlapping the first substrate in a vertical projection direction. The plurality of second electrodes are disposed on the circuit substrate. A distance between the edge of one of the plurality of second electrodes and the edge of one of the plurality of first electrodes is greater than zero in the first direction, and a width of the one of the plurality of first electrodes is different from a width of the one of the plurality of second electrodes.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.

Abstract: According to one example, a method includes performing a first etching process on a fin stack to form a first recess and a second recess at a first depth, the first recess and the second recess on opposite sides of a gate structure that is on the fin stack. The method further includes depositing inner spacers within the first recess and the second recess. The method further includes, after depositing the inner spacers, performing a second etching process to extend a depth of the first recess to a second depth. The method further includes forming a dummy contact region within the first recess, forming a source structure within the first recess on the dummy contact region, and forming a drain structure within the second recess.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

Abstract: An electronic device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; a power line disposed on the substrate, wherein a part of the power line is overlapped with the gate electrode; and a connecting member disposed on the substrate and electrically connected to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, wherein in a top view, an outline of the connecting member includes a first curve section, and an outline of the gate electrode includes a second curve section.

Abstract: The present disclosure relates to a novel mutant form of ?-fucosidase (?-L-fucosidase), which exhibits enhanced ?-(1,6) fucosidase activity. The present disclosure also relates to the compositions comprising the novel mutant form of ?-fucosidase, and the methods of using the novel mutant form of ?-fucosidase to cleave ?-(1,6)-linked fucoses in the glycoconjugates.

Abstract: A substrate assembly is provided, including a first substrate, an active element layer, a plurality of first electrodes, a circuit substrate, and a plurality of second electrodes. The active element layer is disposed on the first substrate. The plurality of first electrodes are disposed on the first substrate and arranged along a first direction. The circuit substrate is partially overlapping the first substrate in a vertical projection direction. The plurality of second electrodes are disposed on the circuit substrate. A distance between the edge of one of the plurality of second electrodes and the edge of one of the plurality of first electrodes is greater than zero in the first direction, and a width of the one of the plurality of first electrodes is different from a width of the one of the plurality of second electrodes.

Abstract: A device includes a substrate, an isolation structure over the substrate, and two fins extending from the substrate and above the isolation structure. Two source/drain structures are over the two fins respectively and being side by side along a first direction generally perpendicular to a lengthwise direction of the two fins from a top view. Each of the two source/drain structures has a near-vertical side, the two near-vertical sides facing each other along the first direction. A contact etch stop layer (CESL) is disposed on at least a lower portion of the near-vertical side of each of the two source/drain structures. And two contacts are disposed over the two source/drain structures, respectively, and over the CESL.

Abstract: The present disclosure relates to a composition for inducing immune response comprising a glycoengineered antibody or antigen-binding fragment thereof that is specific for an antigen portion having a receptor binding domain (RBD) of a surface protein of a virus. The present disclosure also relates to an immune combination and a method for treating an infection by a virus.

Abstract: Disclosed is a topical composition comprising: (i) an antimicrobial active which is at least one of piroctone, caprylhydroxamic acid, benzohydroxamic acid, or piroctone olamine; and (ii) Febrifugine. Also disclosed is a non-therapeutic method of providing topical antimicrobial benefit on a topical surface of a human or animal body comprising a step of applying a safe and effective amount of the topical composition.

Abstract: An electronic device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; a power supply circuit disposed on the substrate; and a connecting member disposed on the substrate and electrically connected to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, wherein in a top view, an outline of the connecting member includes a first curve segment, wherein a maximum width of the data line in a direction perpendicular to the extension direction is less than a maximum width of the power supply circuit in the direction.

Abstract: A semiconductor device includes: a substrate; conductive lines disposed on the substrate, wherein the conductive lines extend along a first direction; a first conductive structure disposed on the substrate, wherein the first conductive structure includes a linear portion extending along a second direction perpendicular to the first direction and a protruding portion connected to and protruding from the linear portion, and the conductive lines cross the linear portion; a second conductive structure disposed on the substrate, wherein the second conductive structure includes a first portion overlapped with the first conductive structure and a second portion not overlapped with the first conductive structure, wherein the second portion of the second conductive structure includes a turning part and an end part, and the end part has a curved shape; and a semiconductor layer disposed on the substrate, wherein the semiconductor layer is overlapped with the second conductive structure.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride and ammonia.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure extended above a substrate along a first direction, and a first gate structure formed over the first fin structure along a second direction. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first fin structure and adjacent to the first gate structure, and a cap layer formed on and in direct contact with the first S/D structure. The semiconductor device structure includes an isolation structure adjacent to the first gate structure and the first S/D structure along the first direction. The isolation structure extends from the first gate structure to the first S/D structure, and the first S/D structure has a protruding portion toward to the isolation structure, and the protruding portion of the first S/D structure is separated from the isolation structure by the cap layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

Abstract: A planar transparent antenna structure is provided. The planar transparent antenna structure includes a dielectric substrate, a radiation conductive layer and a ground conductive layer. The dielectric substrate has a first surface and a second surface. The radiation conductive layer is disposed on the first surface of the dielectric substrate. The ground conductive layer is disposed on the second surface of the dielectric substrate. The radiation conductive layer and the ground conductive layer are composed of a plurality of wires connected in a mesh manner. Each of the wires is composed of a plurality of grid lines connected in a mesh manner.