Patents by Inventor Ching Chu
Ching Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11932714Abstract: A copolymer, a film composition and a composite material employing the same are provided. The copolymer is a copolymerization product of a composition, wherein the composition includes a monomer (a), a monomer (b) and a monomer (c). The monomer (a) is a compound having a structure represented by Formula (I), the monomer (b) is a compound having a structure represented by Formula (II), and the monomer (c) is a compound having a structure represented by Formula (III) wherein R1, R2, R3, R4, R5 and R6 are as defined in specification.Type: GrantFiled: July 22, 2022Date of Patent: March 19, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yen-Yi Chu, Yun-Ching Lee, Li-Chun Liang, Wei-Ta Yang, Hsiang-Chin Juan
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Patent number: 11937426Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.Type: GrantFiled: May 3, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Ching Chu, Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen
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Publication number: 20240086021Abstract: A substrate assembly is provided, including a first substrate, an active element layer, a plurality of first electrodes, a circuit substrate, and a plurality of second electrodes. The active element layer is disposed on the first substrate. The plurality of first electrodes are disposed on the first substrate and arranged along a first direction. The circuit substrate is partially overlapping the first substrate in a vertical projection direction. The plurality of second electrodes are disposed on the circuit substrate. A distance between the edge of one of the plurality of second electrodes and the edge of one of the plurality of first electrodes is greater than zero in the first direction, and a width of the one of the plurality of first electrodes is different from a width of the one of the plurality of second electrodes.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Chia-Hsiung CHANG, Yang-Chen CHEN, Kuo-Chang SU, Hsia-Ching CHU
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Patent number: 11929319Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.Type: GrantFiled: July 22, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
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Publication number: 20240072034Abstract: A method includes bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer, forming a gap-filling region to encircle the first device die, performing a backside-grinding process on the device wafer to reveal a through-via in the second device die, and forming a redistribution structure on the backside of the device wafer. The redistribution structure is electrically connected to the first device die through the through-via in the second device die. A supporting substrate is bonded to the first device die.Type: ApplicationFiled: January 9, 2023Publication date: February 29, 2024Inventors: Ching-Yu Huang, Kuo-Chiang Ting, Ting-Chu Ko
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Patent number: 11917803Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.Type: GrantFiled: July 7, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20240065042Abstract: The disclosure provides a display device, including a first thin film transistor, an insulating layer disposed on the first thin film transistor, a conductive line, and a pixel define layer. The conductive line is electrically coupled to the first thin film transistor via a first contact hole of the insulating layer. The pixel define layer is disposed on the insulating layer. The pixel define layer has a first opening region, a second opening region, and a third opening region. The first opening region and the second opening region are arranged along the first direction. A distance is the shortest distance between the first contact hole and the first opening region. A second distance is the shortest distance between the first contact hole and the second opening region. The first distance is different from the second distance.Type: ApplicationFiled: October 31, 2023Publication date: February 22, 2024Applicant: Innolux CorporationInventors: Hsia-Ching Chu, Pai-Chiao Cheng
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Patent number: 11908748Abstract: A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate and through the isolation feature in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate and through the isolation feature in the second region, and a second epitaxial feature over the second fin. A portion of the isolation feature located between the first fin and the second fin protrudes from a top surface of the isolation feature.Type: GrantFiled: November 15, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 11901236Abstract: An integrated circuit (IC) includes a substrate and a first transistor on the substrate. The first transistor includes two first source/drain features, a stack of first semiconductor layers and second semiconductor layers alternately stacked one over another and disposed between the two first source/drain features, a first gate dielectric layer disposed over top and sidewalls of the stack of the first and the second semiconductor layers, a first gate electrode layer disposed over the first gate dielectric layer, and first spacer features disposed laterally between each of the second semiconductor layers and each of the two first source/drain features and electrically isolating each of the second semiconductor layers from each of the two first source/drain features. The first semiconductor layers electrically connect the two first source/drain features.Type: GrantFiled: May 9, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng-Ching Chu, Wei-Yang Lee, Chia-Pin Lin
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Patent number: 11894421Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.Type: GrantFiled: August 9, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.VInventors: Feng-Ching Chu, Wei-Yang Lee, Yen-Ming Chen, Feng-Cheng Yang
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Patent number: 11878214Abstract: A method for bicycle fitting includes receiving evaluation factors based on one or more scenario parameters; positioning at least one of a saddle and a handlebar to one or more positions when a user is pedaling; determining values for the evaluation factors according to data received from one or more sensors at the one or more positions; and processing the values to identify one or more recommended positions for the saddle or the handlebar.Type: GrantFiled: March 26, 2021Date of Patent: January 23, 2024Assignee: GIANT MANUFACTURING CO., LTD.Inventors: Ya-Han Chang, Chang-Hsin Hsieh, Pei-Min Wu, Yen-Ching Chu, Sheng-Ho Shu, Jun-Rong Chen
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Publication number: 20240014224Abstract: An electronic device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; a power supply circuit disposed on the substrate; and a connecting member disposed on the substrate and electrically connected to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, wherein in a top view, an outline of the connecting member includes a first curve segment, wherein a maximum width of the data line in a direction perpendicular to the extension direction is less than a maximum width of the power supply circuit in the direction.Type: ApplicationFiled: July 5, 2023Publication date: January 11, 2024Inventors: Yun-Sheng CHEN, Hsia-Ching CHU, Ming-Chien SUN
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Patent number: 11862712Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.Type: GrantFiled: November 12, 2020Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Ching Chu, Chung-Chi Wen, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 11861128Abstract: A substrate assembly is provided, including a first substrate and a circuit substrate. The first substrate comprising an edge. An active element layer is disposed on the first substrate. A plurality of first electrodes are disposed on the first substrate and between the edge and an edge of the active element layer, and arranged along a first direction. At least one of the plurality of first electrodes is electrically connected to the active element layer, a first register mark is disposed on the first substrate. The circuit substrate is partially overlapping the first substrate in a vertical projection direction, a plurality of second electrodes is disposed on the circuit substrate.Type: GrantFiled: January 4, 2023Date of Patent: January 2, 2024Assignee: INNOLUX CORPORATIONInventors: Chia-Hsiung Chang, Yang-Chen Chen, Kuo-Chang Su, Hsia-Ching Chu
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Patent number: 11854688Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH3).Type: GrantFiled: May 29, 2020Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 11851691Abstract: The present disclosure provides a fusion protein comprising a fucosidase or a truncated fragment or a mutant thereof fuses with either N-terminal end or C-terminal end of the endoglycosidase or a truncated fragment of mutant thereof. The present disclosure also provides a nucleic acid molecule expressing the fusion protein and a method for remodeling a glycan of an antibody Fc region.Type: GrantFiled: August 5, 2020Date of Patent: December 26, 2023Assignee: CHO PHARMA INC.Inventors: Kuo-Ching Chu, Lin-Ya Huang, Yi-Fang Zeng
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Patent number: 11839677Abstract: Disclosed is a topical composition comprising: (i) an antimicrobial active which is at least one of piroctone, caprylhydroxamic acid, benzohydroxamic acid, or piroctone olamine; and (ii) norbraylin. Also disclosed is a non-therapeutic method of providing topical antimicrobial benefit on a topical surface of a human or animal body comprising a step of applying a safe and effective amount of the topical composition.Type: GrantFiled: June 1, 2021Date of Patent: December 12, 2023Assignee: Conopco, Inc.Inventors: Chung-Ching Chu, Mingming Pu, Zongxiu Wang
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Patent number: 11844245Abstract: The disclosure provides a display device, including a substrate, a plurality of power lines and a pixel define layer. The plurality of power lines disposed on the substrate. The pixel define layer is disposed on the substrate, wherein the pixel define layer includes a first opening region and a second opening region. In a top view, the first opening region is adjacent to the second opening region, the first opening region overlaps a first power line of the plurality of power lines to define a first overlapping area, the second opening region overlaps a second power line of the plurality of power lines to define a second overlapping area, and the first overlapping area is different from the second overlapping area.Type: GrantFiled: April 29, 2022Date of Patent: December 12, 2023Assignee: Innolux CorporationInventors: Hsia-Ching Chu, Pai-Chiao Cheng
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Publication number: 20230389320Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Feng-Ching Chu, Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen
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Patent number: D1012667Type: GrantFiled: May 31, 2022Date of Patent: January 30, 2024Assignee: TONG LUNG METAL INDUSTRY CO., LTD.Inventors: Mei-Ching Chu, Chun-Yi Fang, Suh-You Yang, Shih-Kai Hsu