Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH3).

Abstract: According to one example, a method includes performing a first etching process on a fin stack to form a first recess and a second recess at a first depth, the first recess and the second recess on opposite sides of a gate structure that is on the fin stack. The method further includes depositing inner spacers within the first recess and the second recess. The method further includes, after depositing the inner spacers, performing a second etching process to extend a depth of the first recess to a second depth. The method further includes forming a dummy contact region within the first recess, forming a source structure within the first recess on the dummy contact region, and forming a drain structure within the second recess.

Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures is provided. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Abstract: A display device is disclosed, which includes: a substrate; a scan line disposed on the substrate; a drain electrode, disposed on the substrate and including an arc edge; a first transparent conductive layer disposed on the substrate; and a second transparent conductive layer disposed between the substrate and the first transparent conductive layer, wherein the arc edge is located outside the scan line, and the arc edge is not overlapped with the second transparent conductive layer.

Abstract: Disclosed is a method of determining a bacterial strain suitable for treating a human skin dysbiotic condition, comprising a step of doing network analysis by a computer to determine the connectivity of said bacterial strain with at least a second bacterial strain in a dysbiotic condition as well as a non-dysbiotic condition, wherein there is difference in said connectivity between said dysbiotic condition and said non-dysbiotic condition wherein said connectivity means a positive correlation or negative correlation and further wherein said network is generated by co-occurrence analysis of abundance of said bacterial strain and said second bacterial strain by DNA sequencing by following 16s rRNA amplicon or whole genome sequencing method.

Abstract: An integrated circuit (IC) includes a substrate and a first transistor on the substrate. The first transistor includes two first source/drain features, a stack of first semiconductor layers and second semiconductor layers alternately stacked one over another and disposed between the two first source/drain features, a first gate dielectric layer disposed over top and sidewalls of the stack of the first and the second semiconductor layers, a first gate electrode layer disposed over the first gate dielectric layer, and first spacer features disposed laterally between each of the second semiconductor layers and each of the two first source/drain features and electrically isolating each of the second semiconductor layers from each of the two first source/drain features. The first semiconductor layers electrically connect the two first source/drain features.

Abstract: Methods and apparatuses are disclosed to help the elderly or physically impaired individual standing up from a chair, a bench, a wheel chair, a toilet seat, a commode, a rollator seat, a walker seat, or a car seat. The disclosed apparatus to generate lifting thrust for individual to stand up from a chair has a base, a slidable seat pivoted mounted on the base and a lifting spring to reserve the energy on sitting down and release the saved energy on standing up.

Abstract: The disclosure provides a display device, including a substrate, a plurality of power lines and a pixel define layer. The plurality of power lines disposed on the substrate. The pixel define layer is disposed on the substrate, wherein the pixel define layer includes a first opening region and a second opening region. In a top view, the first opening region is adjacent to the second opening region, the first opening region overlaps a first power line of the plurality of power lines to define a first overlapping area, the second opening region overlaps a second power line of the plurality of power lines to define a second overlapping area, and the first overlapping area is different from the second overlapping area.

Abstract: A fixing device for fixing a display card on a circuit board, includes a backplane and a support bracket. The backplane includes a substrate plate, and a first engaging part. The substrate plate is fixed on the display card. The first engaging part is disposed on the substrate plate. The support bracket includes at least one support leg and a second engaging part. The support leg includes a first end and a second end. The first end is connected with the circuit board. The second engaging part is connected with the second end and engaged with the first engaging part.

Abstract: A display device includes: a substrate; a data line disposed on the substrate; an another data line disposed on the substrate and adjacent to the data line; a first light emitting diode including a first electrode; and a second light emitting diode including an another first electrode, wherein the first electrode partially overlaps the data line, the another first electrode partially overlaps the another data line, and an area of the first electrode and an area of the another first electrode are different.

Abstract: The present invention relates to Use of thymol or terpineol or an analogue of thymol or terpineol in a topical composition el for balancing microbiota of amenable skin, where balancing means selectively reducing microbial count of at least one genus of harmful microbes or of at least one genus of microbes that exhibit abnormal growth, while selectively increasing microbial count of at least one genus of beneficial microbes or of at least one genus of microbes whose numbers have abnormally reduced.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

Abstract: The disclosure provides a display device, including a substrate, a plurality of power lines and a pixel define layer. The plurality of power lines disposed on the substrate. The pixel define layer is disposed on the substrate, wherein the pixel define layer includes a first opening region and a second opening region. In a top view, the first opening region is adjacent to the second opening region, the first opening region overlaps a first power line of the plurality of power lines to define a first overlapping area, the second opening region overlaps a second power line of the plurality of power lines to define a second overlapping area, and the first overlapping area is different from the second overlapping area.

Abstract: A display device includes: a substrate; a data line disposed on the substrate; an another data line disposed on the substrate and adjacent to the data line; a first light emitting diode including a first electrode; and a second light emitting diode including an another first electrode, wherein the first electrode partially overlaps the data line and the another first electrode partially overlaps the another data line.

Abstract: The present disclosure relates to a composition for inducing immune response comprising a glycoengineered antibody or antigen-binding fragment thereof that is specific for an antigen portion having a receptor binding domain (RBD) of a surface protein of a virus. The present disclosure also relates to an immune combination and a method for treating an infection by a virus.

Abstract: An integrated circuit includes a stacked FinFET in a second area and a GAA transistor in a first area. The stacked FinFET includes two first source/drain, first and second semiconductor layers alternately stacked one over another and between the two first source/drain, a first gate dielectric layer over top and sidewalls of the first and second semiconductor layers, a first gate electrode layer over the first gate dielectric layer, and first spacer features laterally between the second semiconductor layers and the two first source/drain. The first and the second semiconductor layers include different materials. The GAA transistor includes two second source/drain, third semiconductor layers electrically connecting the two second source/drain, a second gate dielectric layer wrapping around the third semiconductor layers, a second gate electrode over the second gate dielectric layer, and second spacer features laterally between the second gate dielectric layer and the two second source/drain.