Abstract: An integrated circuit (IC) includes a substrate and a first transistor on the substrate. The first transistor includes two first source/drain features, a stack of first semiconductor layers and second semiconductor layers alternately stacked one over another and disposed between the two first source/drain features, a first gate dielectric layer disposed over top and sidewalls of the stack of the first and the second semiconductor layers, a first gate electrode layer disposed over the first gate dielectric layer, and first spacer features disposed laterally between each of the second semiconductor layers and each of the two first source/drain features and electrically isolating each of the second semiconductor layers from each of the two first source/drain features. The first semiconductor layers electrically connect the two first source/drain features.

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Abstract: A method for bicycle fitting includes receiving evaluation factors based on one or more scenario parameters; positioning at least one of a saddle and a handlebar to one or more positions when a user is pedaling; determining values for the evaluation factors according to data received from one or more sensors at the one or more positions; and processing the values to identify one or more recommended positions for the saddle or the handlebar.

Abstract: An electronic device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; a power supply circuit disposed on the substrate; and a connecting member disposed on the substrate and electrically connected to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, wherein in a top view, an outline of the connecting member includes a first curve segment, wherein a maximum width of the data line in a direction perpendicular to the extension direction is less than a maximum width of the power supply circuit in the direction.

Abstract: A substrate assembly is provided, including a first substrate and a circuit substrate. The first substrate comprising an edge. An active element layer is disposed on the first substrate. A plurality of first electrodes are disposed on the first substrate and between the edge and an edge of the active element layer, and arranged along a first direction. At least one of the plurality of first electrodes is electrically connected to the active element layer, a first register mark is disposed on the first substrate. The circuit substrate is partially overlapping the first substrate in a vertical projection direction, a plurality of second electrodes is disposed on the circuit substrate.

Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH3).

Abstract: The present disclosure provides a fusion protein comprising a fucosidase or a truncated fragment or a mutant thereof fuses with either N-terminal end or C-terminal end of the endoglycosidase or a truncated fragment of mutant thereof. The present disclosure also provides a nucleic acid molecule expressing the fusion protein and a method for remodeling a glycan of an antibody Fc region.

Abstract: Disclosed is a topical composition comprising: (i) an antimicrobial active which is at least one of piroctone, caprylhydroxamic acid, benzohydroxamic acid, or piroctone olamine; and (ii) norbraylin. Also disclosed is a non-therapeutic method of providing topical antimicrobial benefit on a topical surface of a human or animal body comprising a step of applying a safe and effective amount of the topical composition.

Abstract: The disclosure provides a display device, including a substrate, a plurality of power lines and a pixel define layer. The plurality of power lines disposed on the substrate. The pixel define layer is disposed on the substrate, wherein the pixel define layer includes a first opening region and a second opening region. In a top view, the first opening region is adjacent to the second opening region, the first opening region overlaps a first power line of the plurality of power lines to define a first overlapping area, the second opening region overlaps a second power line of the plurality of power lines to define a second overlapping area, and the first overlapping area is different from the second overlapping area.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: A semiconductor device includes a fin stack, a gate structure on the fin stack, a source region on a first side of the gate structure, a drain region on a second side of the gate structure opposite the first side, and a source contact extending to and connecting the source region. The source region and the drain region are asymmetric.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: A solar cell structure includes a semiconductor substrate having a front side and a back side. A pyramid structure is disposed on the front side of the semiconductor substrate. The pyramid structure has an aspect ratio between 0.5-1.2. A front passivation layer is disposed on the pyramid structure. A first anti-reflection layer is disposed on the pyramid structure. The first anti-reflection layer is a multi-layered, graded anti-reflection layer having at least three coating layers. The at least three coating layers comprise a silicon oxynitride layer having a thickness of 15-30 nm and a refractive index between 1.65 and 1.75. The silicon oxynitride layer is an outermost layer of the multi-layered, graded anti-reflection layer.

Abstract: A display device includes: a substrate; a metal layer disposed on the substrate; an insulating layer disposed on the metal layer; and a first light emitting diode including a first electrode disposed on the metal layer, wherein a via hole passes through the insulating layer, the first electrode electrically connects to the metal layer through the via hole, and an outline of the via hole includes an arc edge.

Abstract: Methods and devices formed thereof that include a fin structure extending from a substrate and a gate structure is formed over the fin structure. An epitaxial feature is formed over the fin structure adjacent the gate structure. The epitaxial feature can include a hollow region (or dielectric filled hollow region) in the epitaxial source/drain region. A selective etching process is performed to remove at least a portion of an epitaxial region having a second dopant type to form the hollow area between the first epitaxial portion and the third epitaxial portion.

Abstract: The present invention relates to a novel use of trehalose. More particularly the present invention relates to a novel use of trehalose for promoting scalp health. Accordingly, the present invention provides use of trehalose as prebiotic for inhibiting ailment inducing microorganisms when applied on an external surface of a human body.

Abstract: The disclosed display device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; and a connecting member disposed on the substrate and electrically connecting to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, and a minimum width of the second part in a direction perpendicular to the extension direction is less than a maximum width of the first part in the direction.