Abstract: A nucleic acid detection kit includes a kit body, a detection chip disposed in the kit body, and an electrophoresis box disposed outside of the kit body. The detection chip comprises a channel and is connected to the electrophoresis box. A microbead of testable material in solution undergoes a PCR amplification reaction, an electrophoretic process, and is fluoresced for highlighting, images of elements made fluorescent can be taken and displayed. A nucleic acid detection device which can receive the nucleic acid detection kit is also disclosed. The nucleic acid detection device has a simple structure suitable for home use, being portable, flexible, and convenient.

Abstract: A pixel circuit including a compensation circuit, a writing circuit, a light emitting element, and a power supplying circuit is provided. The compensation circuit comprises a first node, and provides a driving current to the light emitting element according to a voltage of the first node and a system high voltage. The writing circuit provides a data voltage to the compensation circuit according to a first control signal so that the compensation circuit sets the voltage of the first node. The power supplying circuit selectively couples the compensation circuit to the light emitting element, and provides the system high voltage and a system low voltage to the compensation circuit, in which the system low voltage is configured to reset the voltage of the first node. The first control signal and the second control signal are opposite to the first emission signal and the second emission signal, respectively.

Abstract: An integrated circuit includes a stacked FinFET in a second area and a GAA transistor in a first area. The stacked FinFET includes two first source/drain, first and second semiconductor layers alternately stacked one over another and between the two first source/drain, a first gate dielectric layer over top and sidewalls of the first and second semiconductor layers, a first gate electrode layer over the first gate dielectric layer, and first spacer features laterally between the second semiconductor layers and the two first source/drain. The first and the second semiconductor layers include different materials. The GAA transistor includes two second source/drain, third semiconductor layers electrically connecting the two second source/drain, a second gate dielectric layer wrapping around the third semiconductor layers, a second gate electrode over the second gate dielectric layer, and second spacer features laterally between the second gate dielectric layer and the two second source/drain.

Abstract: A solar cell structure includes a semiconductor substrate having a front side and a back side; a pyramid structure disposed on the front side of the semiconductor substrate; a front passivation layer disposed on the pyramid structure; and a first anti-reflection layer disposed on the pyramid structure. The first reflective layer is a multi-layered anti-reflection layer having at least three coating layers. A front electrode is provided on the first anti-reflection layer. A rear passivation layer is provided on the back side of the semiconductor substrate. A second anti-reflection layer is disposed on the rear passivation layer. A back electrode is disposed on the second anti-reflection layer.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.

Abstract: The present invention provides a housing having a housing shell with an opening, a guidance component and a door leaf set. The guidance component is arranged in the housing shell and extending along the direction away from the opening. The door leaf set has a first door leaf and a second door leaf. The first door leaf is pivotally connected the housing shell to enable the first door leaf to rotate to a first position or a second position relative to the opening. Wherein when the first door leaf is positioned at the first position, the first door leaf shields a portion of the opening; when the first door leaf is positioned at the second position, the first door leaf extends into the housing shell and defines the first installation space with the guiding component.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first device region and a second device region, a first fin over the substrate in the first device region, a second fin over the substrate in the second device region, a first epitaxial feature over the first fin in the source/drain region of the first fin, a second epitaxial feature over the second fin in the source/drain region of the second fin, and a dielectric layer on the first and second epitaxial features. The first epitaxial feature is doped with a first dopant of a first conductivity and the second epitaxial feature is doped with a second dopant of a second conductivity different from the first conductivity. The dielectric layer is doped with the first dopant.

Abstract: A display device includes: a substrate; a scan line disposed on the substrate; a common electrode disposed on the substrate and including a through hole having a curved edge, wherein the through hole and at least a portion of the scan line are overlapped; a pixel electrode disposed on the substrate and including a slit; and an active layer disposed on the substrate, wherein the active layer and at least a portion of the slit are overlapped.

Abstract: A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: A solar cell structure includes a semiconductor substrate having a front side and a back side; a pyramid structure disposed on the front side of the semiconductor substrate; a anti-reflection layer disposed on the pyramid structure; a front electrode provided on the anti-reflection layer; a passivation layer provided on the back side of the semiconductor substrate; a dielectric layer disposed on the passivation layer; and a back electrode disposed on the dielectric layer. The reflective layer is a multi-layer anti-reflection layer having at least three coating layers.

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Abstract: The disclosed display device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; and a connecting member disposed on the substrate and electrically connecting to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, and a minimum width of the second part in a direction perpendicular to the extension direction is less than a maximum width of the first part in the direction.

Abstract: A method for bicycle fitting includes receiving evaluation factors based on one or more scenario parameters; positioning at least one of a saddle and a handlebar to one or more positions when a user is pedaling; determining values for the evaluation factors according to data received from one or more sensors at the one or more positions; and processing the values to identify one or more recommended positions for the saddle or the handlebar.

Abstract: This invention relates to an antimicrobial composition, especially one which provides synergistic anti-dandruff efficacy. This is achieved through a judicious combination of anti-dandruff agent zinc pyrithione and select antimicrobial lipids. These compositions can be delivered through shampoo or conditioner. Disclosed is an anti-microbial composition comprising: (i) 0.1 to 3% by weight of zinc pyrithione; (ii) 0.01 to 5.0% by weight of an antimicrobial lipid selected from sapienic acid, palmitoleic acid, sphingosine, dihydrosphingosine, and phytosphingosine; and a cosmetically acceptable vehicle, wherein said composition is a shampoo or a conditioner for preventing or alleviating the symptoms of dandruff on the scalp and/or hair and where an antimicrobial alcohol having 1 to 7 carbon atoms are absent from the composition.

Abstract: Methods and devices formed thereof that include a fin structure extending from a substrate and a gate structure is formed over the fin structure. An epitaxial feature is formed over the fin structure adjacent the gate structure. The epitaxial feature can include a hollow region (or dielectric filled hollow region) in the epitaxial source/drain region. A selective etching process is performed to remove at least a portion of an epitaxial region having a second dopant type to form the hollow area between the first epitaxial portion and the third epitaxial portion.

Abstract: A method includes etching two source/drain regions over a substrate to form two source/drain trenches; epitaxially growing two source/drain features in the two source/drain trenches respectively; performing a cut process to the two source/drain features; and after the cut process, depositing a contact etch stop layer (CESL) over the two source/drain features.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.