Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate disposed on a substrate, a dielectric layer and two charge trapping layers, wherein the dielectric layer is disposed between the substrate and the memory gate, and the two charge trapping layers are disposed at two opposite sides of the memory gate, wherein each of the charge trapping layers comprises an L-shape cross-sectional profile, and two selective gates disposed on the substrate, thereby constituting a two bit memory cell, wherein a top surface of each selective gate is higher than a top surface of the memory gate.

Abstract: A high-speed connector includes an insulating housing, a first terminal assembly received in the insulating housing, a second terminal assembly received in the insulating housing, a third terminal assembly received in the insulating housing, and a fourth terminal assembly received in the insulating housing. The second terminal assembly is opposite to the first terminal assembly along an up-down direction. The third terminal assembly is disposed between the first terminal assembly and the second terminal assembly. The fourth terminal assembly is corresponding to the third terminal assembly. The fourth terminal assembly is disposed between the second terminal assembly and the third terminal assembly.

Abstract: A package component includes an insulating substrate, a semiconductor structure, a first conductive line and a conductive pad. The semiconductor structure is disposed in the insulating substrate and separated from the insulating substrate. The first conductive line is disposed on a first side of the insulating substrate. The conductive pad is disposed on a first side of the semiconductor structure. The first conductive line and the conductive pad include a same material. A surface roughness of the conductive pad is greater than a surface roughness of the first conductive line.

Abstract: A semiconductor structure includes a conductive bump disposed between a substrate and a board; an isolation member disposed over the board and surrounding the conductive bump and the substrate; a metallic member disposed between the isolation member and the conductive bump; and a solder disposed between the substrate and the board and configured to attach the metallic member to the substrate and the board. A method of manufacturing a semiconductor structure includes disposing a first solder on a first surface of a substrate; disposing a metallic member to the first surface of the substrate by the first solder; disposing a second solder on a board; and bonding the metallic member to the board by the second solder.

Abstract: Semiconductor package and method of manufacturing are presented herein. In an embodiment, a device is provided that includes a first semiconductor component embedded in a first core substrate, a first redistribution layer on a first side of the first core substrate, a second redistribution layer on a second side of the first core substrate opposite the first side, a first resin film over the second redistribution layer, a second semiconductor component embedded in a second core substrate, a third redistribution layer on a third side of the second core substrate, wherein the third redistribution layer is bonded to the second redistribution layer by the first resin film, a fourth redistribution layer on a fourth side of the second core substrate opposite the third side, and a through hole via extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer.

Abstract: Methods and pad structures to test via accuracy are provided. A method according to the present disclosure includes forming a first pad and a second pad on a device component, wherein the second pad includes a via landing area and a clearance opening, providing a core substrate that includes a cavity, placing the device component in the cavity, forming a build-up film over the device component and the core substrate, forming a first contact via extending through the build-up film to contact the landing area and a second contact via extending through build-up film and the clearance opening, and performing a continuity test to determine whether the second contact via is in contact with the second pad.

Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a first movable portion used for connecting an optical element, a fixed portion, a first driving assembly used for driving the first movable portion to rotate relative to the fixed portion, and a guiding assembly having a first intermediate element. The first movable portion is movable relative to the fixed portion. The guiding assembly is used for applying a first stabilized force to the first movable portion for making the first intermediate element be in contact with the first movable portion or the fixed portion. The first movable portion is rotatable relative to the fixed portion.

Abstract: A motor stator winding structure includes a stator core and slot-positions. The stator core includes an insertion side and an extension side. The hairpin wires are configured to be arranged into slot-positions of the phase slots of the same phases of the polar regions. A first phase winding includes first hairpin wires of the hairpin wires inserted from an entry phase slot-position of a first phase. A second phase winding includes second hairpin wires of the hairpin wires inserted from an entry phase slot-position of a second phase. A third phase winding includes third hairpin wires of the hairpin wires inserted from an entry phase slot-position of a third phase. The entry phase slot-position of the first phase, the entry phase slot-position of the second phase and the entry phase slot-position of the third phase are located in three different polar regions respectively.

Abstract: A high-speed connector includes an insulating housing, and at least one terminal assembly disposed in the insulating housing. The at least one terminal assembly includes a base body, a plurality of terminals fastened to the base body, and a metal block. A surface of the base body is recessed inward to form a fastening groove. The plurality of the terminals include a plurality of grounding terminals and differential signal terminals. Each of the plurality of the grounding terminals and the differential signal terminals has a fastening portion. The fastening portions of at least several of the plurality of the grounding terminals and the differential signal terminals are exposed to the fastening groove. The metal block is fastened in the fastening groove. The fastening portions of the grounding terminals which are exposed to the fastening groove are electrically connected with the metal block to form a grounding structure.

Abstract: An electrical connector for mounting on an external circuit board includes: an insulating body; a terminal module assembled on the insulating body and including a plurality of mating terminals, an insulating carrier with an accommodating cavity, plural intermediate terminals fixed on one side of the insulating carrier and electrically connected to the mating terminals, plural pin terminals fixed on the other side of the insulating carrier, and a magnetic module accommodated in the accommodating cavity and electrically connected to the intermediate terminals and the pin terminals, wherein the insulating carrier is a two-piece housing, the intermediate terminals are held in one housing piece, and the pin terminals are held in the other housing piece.

Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

Abstract: A thermoplastic polyurethane resin used for preparing a car wrap film is formed from a reaction mixture through a polymerization reaction. The reaction mixture includes: an isocyanate material, a polyol material, and a chain extender. The isocyanate material does not have any benzene ring in its chemical structure. The isocyanate material is selected from the group consisting of 4,4?-diisocyanato dicyclohexylmethane (H12MDI), hexamethylene diisocyanate (HDI), and isophorone diisocyanate (IPDI). The polyol material is selected from the group consisting of polycaprolactone polyol and polyether polyol. The chain extender is a glycol chain extender.

Abstract: An electronic device includes a light guide plate, a back plate, a plurality of light sources, an optical film and a buffer member. The back plate accommodates the light guide plate and includes a bottom plate, a side plate, a bending portion and a first notch portion, wherein a side of the bending portion and a side of the bottom plate are respectively connected to opposite sides of the side plate, the bending portion is overlapped with the bottom plate, the first notch portion is adjacent to the bending portion, and the first notch portion is overlapped with the bottom plate. The light sources are disposed between the bottom plate and the bending portion. The optical film is disposed on the light guide plate and is separated from the bending portion. The buffer member is overlapped with the first notch portion and the light guide plate.

Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a first movable portion, a fixed portion, a first driving assembly, and a plurality of second guiding members. The first movable portion is configured to connect an optical member. The optical member is used for adjusting a direction of a light from an incident direction to an outgoing direction. The first movable portion can move relative to the fixed portion. The first driving assembly is configured to drive the first movable portion to move relative to the fixed portion. The second guiding members include a first ball, a second ball, and a third ball. The first ball, the second ball, and the third ball are disposed in a plane that is perpendicular to the incident direction.

Abstract: An electrical connector for mounting on an external circuit board includes: an insulating body having an upper receiving space and a lower receiving space; a terminal module assembled on the insulating body and including plural pin terminals, each pin terminal having a pin for mounting on the external circuit board, wherein the terminal module is capable of being modified to support 1G or 2.5G or 5G or 10G or 25G or 40G signal transmission while keeping arrangement pattern of the pins unchanged in order to be mounted on the same external circuit board.

Abstract: A method for producing Si ingot single crystal including a Si ingot single crystal growing step, a temperature gradient controlling step and a continuous growing step is provided. In the growing step, the Si ingot single crystal is grown in silicon melt in crucible, and the growing step includes providing a low-temperature region in the Si melt and providing a silicon seed to contact the melt surface of the silicon melt to start crystal growth, and silicon single crystal grows along the melt surface of the silicon melt and toward the inside of the silicon melt. In the temperature gradient controlling step, the under-surface temperature gradient of the silicon single crystal is G1, the above-surface temperature gradient of the silicon single crystal is G2, G1 and G2 satisfy: G2/G1<6. The step of controlling the temperature gradient of silicon single crystal is repeated to obtain the Si ingot single crystal.

Abstract: A semiconductor memory device includes a substrate; a first dielectric layer on the substrate; and bottom electrodes on the first dielectric layer. The bottom electrodes are arranged equidistantly in a first direction and extend along a second direction. A second dielectric layer is disposed on the first dielectric layer. Top electrodes are disposed in the second dielectric layer and arranged at intervals along the second direction. Each top electrode includes a lower portion located around each bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrodes and around the tapered upper portion. A resistive-switching layer is disposed between a sidewall of each bottom electrode and a sidewall of the lower portion and between the third dielectric layer and a sidewall of the tapered upper portion. An air gap is disposed in the third dielectric layer.

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.

Abstract: Methods of conducting electrical tests on semiconductor packages are provided. A method according to the present disclosure includes forming a build-up structure that includes a plurality of metal layers embedded a plurality of dielectric layers, forming a core structure that embeds a passive device, performing a first electrical test on the build-up structure, performing a second electrical test on the core structure, and after performing the first electrical test and the second electrical test, bonding the build-up structure to the core structure.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate having a pad and a conductive adhesive layer over the pad and having a first inner wall, a second inner wall, a first sidewall, and a second sidewall. The first inner wall and the second inner wall face each other, and the first sidewall and the second sidewall are opposite to each other. The chip package structure also includes a nickel layer over the conductive adhesive layer, and the nickel layer covers the first inner wall, the second inner wall, the first sidewall, and the second sidewall of the conductive adhesive layer. The chip package structure further includes a chip over the wiring substrate and a conductive bump connected between the nickel layer and the chip.