Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a nickel layer over the first pad. The nickel layer has a T-shape in a cross-sectional view of the nickel layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip.

Abstract: Disclosed is a method for manufacturing a reinforced synthetic product with a curved geometry, which includes forming a fabric made of at least one filament bundle including a reinforcing fiber material and at least one thermoplastic filament woven with the filament bundle; and combining a heat-formable material with the fabric to form a bendable fabric preform sheet. Also disclosed is a method for manufacturing a reinforced synthetic product with a curved geometry, which includes positioning the bendable fabric preform sheet into a mold with a curved geometry to form a bended fabric preform sheet; and molding the bended fabric preform sheet by heating to form a cured product.

Abstract: A polyurethane adhesive and a mixture used for manufacturing a plastic athletic track are provided. The polyurethane adhesive includes a urethane pre-polymer which is formed by a reaction between an isocyanate and a polyol. The polyol is selected from the group consisting of polyether polyol and polybutadiene polyol, and a number average molecular weight of the polyol is between 1,000 g/mole and 6,000 g/mole. Based on the total weight of the polyurethane adhesive, a content of the urethane pre-polymer is between 80 wt % and 99.5 wt %, and a viscosity of the polyurethane adhesive is between 1,000 cps and 3,000 cps under an environmental temperature of between 15° C. and 40° C.

Abstract: A method for producing Si ingot single crystal by NOC growth method including a Si ingot single crystal growing step and a continuous growing step is provided. The growing step includes providing a low temperature region in the Si melt where the Si ingot single crystal is grown along the surface of the Si melt or toward the inside of the Si melt, and the Si ingot single crystal has distribution of a vacancy concentration and an interstitial concentration in which respectively a vacancy concentration and an interstitial concentration vary with a distance from the growth interface; and adjusting a temperature gradient and a growth rate in the Si melt, so that along with the increasing of the distance from the growth interface, the vacancy concentration and the interstitial concentration in the Si ingot single crystal respectively decrease come near to each other.

Abstract: A method for producing Si ingot single crystal by NOC growth method including a Si ingot single crystal growing step and a continuous growing step is provided. The growing step includes providing a low temperature region in the Si melt where the Si ingot single crystal is grown along the surface of the Si melt or toward the inside of the Si melt, and the Si ingot single crystal has distribution of a vacancy concentration and an interstitial concentration in which respectively a vacancy concentration and an interstitial concentration vary with a distance from the growth interface; and adjusting a temperature gradient and a growth rate in the Si melt, so that along with the increasing of the distance from the growth interface, the vacancy concentration and the interstitial concentration in the Si ingot single crystal respectively decrease come near to each other.

Abstract: An electronic device includes a light guide plate, a plurality of light sources, a sealant frame and at least an optical film. The light guide plate includes a first end portion and a second end portion opposite to each other. The plurality of light sources are disposed adjacent to the second end portion and are arranged along the first direction. The sealant frame is disposed adjacent to the first end portion. One of the at least an optical film includes a body portion and a lug portion connected to the body portion, and the lug portion is fixed on the sealant frame. The body portion includes a first side adjacent to the sealant frame and, in a second direction, a shortest distance between the first side and the sealant film is in a range of 0 mm to 0.4 mm.

Abstract: A resin composition suitable for profile extrusion processing is provided. Based on the total weight of the resin composition, the resin composition includes 40 wt. % to 92.1 wt. % of polyester; 2 wt. % to 15 wt. % of modifier, 0.2 wt. % to 1.5 wt. % of tackifier, and 0.1 wt. % to 40 wt. % of filler.

Abstract: A wafer and a wafer processing method are included. The wafer processing method includes the following steps. A wafer is provided having a first surface and a second surface opposite to the first surface. A fixture pattern is pasted on the first surface to cover a first portion of the first surface of the wafer, and a second portion of the first surface is exposed by the fixture pattern. A first etching step is performed on the second portion of the first surface to form a first etching pattern on the first surface of the wafer. The fixture pattern is removed from the first surface, and the second surface of the wafer is ground.

Abstract: A thermoplastic polyurethane resin suitable for melt spinning is formed from a reaction mixture via a polymerization reaction. The reaction mixture includes an isocyanate component and a polyol component. The polyol component includes a first polyol that has a first number average molecular weight and a second polyol that has a second number average molecular weight. The first number average molecular weight is between 1,000 g/mol and 1,500 g/mol, and the second number average molecular weight is between 2,500 g/mol and 3,000 g/mol. One resin component formed by the first polyol via the polymerization reaction is defined as a low melting point segment and correspondingly has a first melting point between 170° C. and 185° C. Another resin component formed by the second polyol via the polymerization reaction is defined as a high melting point segment and correspondingly has a second melting point between 195° C. and 210° C.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a conductive adhesive layer over the first pad. The conductive adhesive layer is in direct contact with the first pad. The chip package structure includes a nickel layer over the conductive adhesive layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip. The conductive bump includes gold.

Abstract: A mono-crystalline silicon growth apparatus is provided. The mono-crystalline silicon growth apparatus includes a furnace, a support base disposed in the furnace, a crucible disposed on the support base, and a heating module. The support base and the crucible do not rotate relative to the heating module, and an axial direction is defined to be along a central axis of the crucible. The heating module is disposed at an outer periphery of the support base and includes a first heating unit, a second heating unit, and a third heating unit. The first heating unit, the second heating unit, and the third heating unit are respectively disposed at positions with different heights corresponding to the axial direction.

Abstract: A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.

Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

Abstract: An extruder and a long fiber thermoplastic (LFT) extrusion member manufactured thereby, and the extruder uses the LFT as a raw material to produce LFT extrusion members such as LFT sheets, pipes and profiles by a continuous extrusion molding process. The structural improvement of the extruder screw, including the screw body having three different thread groove deep sections, in sequence, a feed section, a compression section and a metering section, so that the LFT extrusion member produced by the extruder has high strength, high stiffness, high dimensional stability, low warpage and resistance to creep.

Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

Abstract: A method for scanning bad block of a memory and a circuit system thereof are provided. In a procedure of scanning bad blocks of the memory, the circuit system uses a cache read command that is adapted to a process of continuously reading a plurality of memory pages of the memory. The cache read command loads a memory page data to a cache of the memory in advance, and then reads the memory page data from the cache at a next instruction cycle. Next, the cache read command loads a next memory page data to the cache. These steps are repeated until the procedure of scanning bad blocks of the memory is completed. The method can effectively reduce the time for the memory to prepare the next page data so as to reduce the impact of the busy time of the memory on time performance.

Abstract: The present invention relates to a tool-free unlocking mechanism including a connecting member and a mounting member, wherein the connecting member has at least one mounting hole that can be placed on the mounting member, and the tool-free unlocking mechanism can be quickly positioned on a bracket.

Abstract: A method of manufacturing an epitaxy substrate is provided. A handle substrate is provided. A beveling treatment is performed on an edge of a device substrate such that a bevel is formed at the edge of the device substrate, wherein a thickness of the device substrate is greater than 100 ?m and less than 200 ?m. An ion implantation process is performed on a first surface of the device substrate to form an implantation region within the first surface. A second surface of the device substrate is bonded to the handle substrate for forming the epitaxy substrate, wherein a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate, and a projection length of the bevel toward the handle substrate is between 600 ?m and 800 ?m.

Abstract: A high-speed connector includes an insulating housing, and at least one terminal assembly disposed in the insulating housing. The at least one terminal assembly includes a base body, a plurality of terminals fastened to the base body, and a metal block. A surface of the base body is recessed inward to form a fastening groove. The plurality of the terminals include a plurality of grounding terminals and differential signal terminals. Each of the plurality of the grounding terminals and the differential signal terminals has a fastening portion. The fastening portions of at least several of the plurality of the grounding terminals and the differential signal terminals are exposed to the fastening groove. The metal block is fastened in the fastening groove. The fastening portions of the grounding terminals which are exposed to the fastening groove are electrically connected with the metal block to form a grounding structure.

Abstract: A method for producing Si ingot single crystal including a Si ingot single crystal growing step, a temperature gradient controlling step and a continuous growing step is provided. In the growing step, the Si ingot single crystal is grown in silicon melt in crucible, and the growing step includes providing a low-temperature region in the Si melt and providing a silicon seed to contact the melt surface of the silicon melt to start crystal growth, and silicon single crystal grows along the melt surface of the silicon melt and toward the inside of the silicon melt. In the temperature gradient controlling step, the under-surface temperature gradient of the silicon single crystal is G1, the above-surface temperature gradient of the silicon single crystal is G2, G1 and G2 satisfy: G2/G1<6. The step of controlling the temperature gradient of silicon single crystal is repeated to obtain the Si ingot single crystal.