Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.

Abstract: A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films, a plurality of second films and at least one doped layer, and the first films and the second films are alternately stacked on the initial layer, wherein the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.

Abstract: An ultra-wideband antenna device is disposed on a casing of an electronic device. The ultra-wideband antenna device includes radio frequency terminals, a first antenna module, a second antenna module, and a switch module. The radio frequency terminals, the first antenna module and the switch module are located in the casing. The first antenna module is located on a metal frame of the casing, and the first antenna module includes a first antenna. The second antenna module includes a second antenna, a third antenna, and a fourth antenna. The switch module is connected between the radio frequency terminals and the first antenna module. When the switch module turns on one of the radio frequency terminals and the first antenna for distance measurement, the switch module selectively turns on at least one of the second antenna, the third antenna, or the fourth antenna.

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.

Abstract: A light sensor structure and the manufacturing method thereof are disclosed. The light sensor structure includes a substrate with a first surface and a second surface opposite to each other. A light sensing element including a light sensing area is disposed on the first surface. A reflection layer is disposed on the second surface. The reflection layer covers a portion of the second surface aligning with the light sensing area.

Abstract: A high-speed connector includes an insulating housing, and a first terminal assembly mounted in the insulating housing. The first terminal assembly includes a plurality of first terminals, a first base body and a first conductive film. The plurality of the first terminals include at least two first grounding terminals and at least two first signal terminals. At least one portion of a bottom of the first base body extends downward to form at least one first protruding portion. The at least two first signal terminals penetrate through the at least one first protruding portion. The first conductive film is covered to the at least one first protruding portion. The first conductive film has a first metal layer. The first metal layer is electrically connected with the at least two first grounding terminals to form a grounding structure.

Abstract: A laser-less packaging substrate fabrication process is provided. A substrate plate including through-plate metal via structures is provided. At least one interconnect-level structure may be formed by performing a unit sequence of processing steps that includes: a metal seed deposition step; a first masking step; a first electroplating step that forms metal lines; a second masking step; a second electroplating step that forms metal via structures; a seed layer etch step; a dielectric material deposition step that forms a dielectric material layer; and a planarization step that removes portions of the dielectric material layer that are more distal from the substrate plate than distal horizontal surfaces of the metal via structures. Laser drilling processing steps are not necessary during manufacture of the packaging substrate.

Abstract: A material analysis method is provided. A plurality of wafers processed from a plurality of ingots are measured by a measuring instrument to obtain an average of a bow of each of the wafers processed from the ingots and a plurality of full widths at half maximum (FWHM) of each of the wafers. Key factors respectively corresponding to the ingots are calculated according to the FWHM of the wafers. A regression equation is obtained according to the key factors and the average of the bows.

Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

Abstract: A method for preparing a fiber-containing molding compound includes the acts of a) providing a composite material which includes a first resin and fibers impregnated with the first resin, and b) mixing the composite material with a treatment medium which includes a diluent to form a mixture. The fiber-containing molding compound thus prepared has an adjustable fiber content.

Abstract: A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.

Abstract: A liquid crystal display has position-adjustable light sources. The light sources may be lamps, LEDs, or other emissive components. The light sources, however, are movable to adjust the locations or positions of their light outputs. The light sources ride upon electromagnet carriers. When currents are applied to the electromagnet carriers, each electromagnet carrier creates a corresponding magnetic field. The magnetic fields cause neighboring electromagnet carriers to attract or to repel, depending on the magnitude/polarity of the currents. The lateral and vertical positions of the electromagnet carriers may thus be adjusted by varying their respective currents and magnetic fields. Because the light sources ride on the electromagnet carriers, the light sources may be moved to refine an image generated by the liquid crystal display. The light sources, for example, may be moved to improve white/black contracts to reduce halo-effects.

Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.

Abstract: An integrated circuit (IC) structure includes a plurality of first metal segments in a first metal layer of a semiconductor substrate, the plurality of first metal segments corresponding to first tracks, a plurality of second metal segments in a second metal layer of the semiconductor substrate adjacent to the first metal layer, the plurality of second metal segments corresponding to second tracks perpendicular to the first tracks, and a plurality of via structures configured to electrically connect the plurality of first metal segments to the plurality of second metal segments.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: An electrical connector includes an insulating body and first through eighth terminals sequentially arranged in a lateral direction in the insulating body, wherein the first and second terminals, the third and sixth terminals, the fourth and fifth terminals, and the seventh and eighth terminals are respectively used to transmit a pair of differential signals, each terminal including: a mating portion for mating to a mating connector; a tail portion opposite to the mating portion; and a connecting portion connected therebetween, the connecting portions of the third terminal to the fifth terminal are all provided with a coupling portion; wherein the coupling portions of the third through fifth terminals are in three different planes, respectively, and the coupling portion of the fifth terminal and the coupling portion of the third terminal at least partially overlap in a longitudinal direction perpendicular to the lateral direction.

Abstract: An electrical connector includes a terminal module having a circuit board having first through eighth conductive traces sequentially arranged in a transverse direction and corresponding first through eighth terminals, the third terminal and the sixth terminal being configured for transmitting a pair of differential signals, the fourth terminal and the fifth terminal being configured for transmitting another pair of differential signals, the first through eighth conductive traces being respectively electrically connected to corresponding first through eighth terminals, each of the third conductive trace and the fifth conductive trace including a coupling portion, a size of the coupling portion in the transverse direction is larger than a size of the other part of the corresponding conductive trace in the transverse direction, wherein the coupling portion of the third conductive trace and the coupling portion of the fifth conductive trace overlap in an up and down direction to increase mutual coupling.

Abstract: Aspects of the subject disclosure may include, for example, identifying a flow of data packets between first and second network addresses of a network, with each packet including respective header and payload portions. The identified flow of data packets is monitored over a number of sample periods to obtain a number of monitored results. A data-flow activity record is generated, having a number of symbols corresponding to the number of monitored results, the symbols including an active symbol value indicative of a presence of an exchange of data and an idle symbol value indicative of an absence of an exchange of data. A suitability of the identified data flow is inferred for estimating a throughput of the network according to the data-flow activity record without interpreting contents of each respective packet payload portion. Other embodiments are disclosed.