Patents by Inventor Chou

Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6200159
    Abstract: A multi-deck electric outlet assembly, which includes a base, a body mounted on the base, the body having a series of steps raised one above another at one side, and a landing at the topside thereof, the steps each having a sloping riser, multiple electric socket units respectively installed in the landing and the risers of the steps and respectively connected to a circuit board at the base, and a power cable inserted through a wire hole on the base and connected to the circuit board.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: March 13, 2001
    Inventor: Jonie Chou
  • Patent number: 6200110
    Abstract: An air compressor includes a housing having a tube extended from the top and having a passage communicating the housing with the tube and having a tapered surface. A piston is slidably received in the chamber of the housing and is forced to move along the housing in a reciprocating action and to force the air out through the tube via the passage. The provision of the tapered surface allows the piston to smoothly move in the housing. A stop is adjustably spring-biased to block the passage. The piston has a spring blade to block an aperture to control the air into the housing.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: March 13, 2001
    Inventor: Wen San Chou
  • Patent number: 6201435
    Abstract: A reference voltage generation circuit has a start-up circuit that will force the reference voltage generation circuit to assume a normal operation mode producing the desired reference voltage level and will reduce noise coupled from a power supply voltage source. The start-up circuit for reference voltage generation circuit will be disabled when a sensing circuit has determined that the reference voltage generation circuit has attained the desired reference voltage level.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: March 13, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Yung-Fa Chou
  • Patent number: 6200191
    Abstract: A motion toy includes a toy body having an upper part and a lower part pivotally connected together, and a power drive coupled between the upper part and the lower part of the toy body. The power drive is controlled to tilt the upper part and the lower part of the toy body alternatively inward and outward in reversed directions.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: March 13, 2001
    Assignee: Blue Ridge Designs, Inc.
    Inventor: Jin-Long Chou
  • Patent number: 6197664
    Abstract: A method for plating conductive material in through apertures and blind apertures of a substrate which has a conductive material on its upper and lower surfaces. In a typical configuration for plating a via, there is a first region of conductive material adjacent to, but outside of, the aperture which forms the via and a second region of conductive material inside of the aperture. The second conductive region is selected to be the cathode of the plating process. The structure is placed in a plating bath, a first potential is applied to the first region of conductive material, and a second potential is applied to the second region of conductive material, with the second potential being different from the first potential. Under these conditions, material will plate onto the second region of conductive material to fill the aperture.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: March 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Michael G. Lee, Michael G. Peters, William T. Chou
  • Patent number: 6195807
    Abstract: A lens combination is provided for a pair of swimming/diving goggles having a goggle frame. The lens combination includes a planar lens mounted to the goggle frame and a curved lens mounted in front of the planar lens, thereby defining a space between the planar lens and the curved lens for receiving water. The curved lens includes an outer surface and an inner surface. The planar lens includes an outer surface and an inner surface. The space is filled with water. When the lens combination is used in water such that the outer surface of the curved lens, the inner surface of the curved lens, and the outer surface of the planar lens contact with water, thereby allowing formation of clear image when viewing an object in water.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: March 6, 2001
    Inventor: Terry Chou
  • Patent number: 6198053
    Abstract: An improved foldable pushbutton-input device conformable to human body mechanism, wherein a plurality of assembly-jointing sections is defined by a plurality of properly spaced predetermined cutting lines on a baseboard; a circuit board made of a flexible material having a plurality of pushbutton-input circuit sections in positions corresponding with the assembly-jointing sections and also defined by the same cutting lines is attached on the baseboard; a signal-output circuit section is formed by extending the lateral edges of the pushbutton-input circuit sections and connected therewith; and a plurality of amount predetermined key sets is disposed on the circuit board or on the baseboard in virtue of the division cutting lines to thereby construct the foldable pushbutton-input device with a considerably reduced volume.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: March 6, 2001
    Assignee: Shin Jiuh Corp.
    Inventor: Chin-Wen Chou
  • Patent number: 6193527
    Abstract: An electrical connector includes a housing formed with at least one row of terminal-receiving cavities and a plurality of terminals. Each of the terminals has a horizontal terminal part which is received in a corresponding one of the cavities and a vertical terminal part which is perpendicular to the horizontal terminal part. The housing has a rear wall which is formed with a horizontally extending supporting rib that is located below the cavities and that has a free end. The vertical terminal parts of the terminals abut against the free end of the supporting ribs so as to ensure the vertical terminal parts of the terminals to be coplanar. The ribs include outer slot portions that receive vertical terminal parts and inner slot portions that receive contact protrusions.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: February 27, 2001
    Inventor: Chou Hsuan Tsai
  • Patent number: 6195484
    Abstract: A method and an apparatus for stretching an optical pulse and shaping its spectrum. The method includes the step of: providing a an optical fiber element having a first long length fiber Bragg grating having a refractive index perturbation of varying periodicity. The optical pulse is launched into the fiber Bragg grating, wherein the Bragg grating reflects the pulse in a chromatically dispersed output. The reflected output is coupled with an optical modulator programmed to temporally modify the amplitude of the chromatically dispersed output to attenuate selected optical frequencies in a desired pattern. The apparatus for stretching and arbitrarily shaping the spectrum of an optical pulse with a desired wavelength resolution &Dgr;&lgr;res includes a routing optical device and an optical fiber element having a Bragg grating. The routing optical device routs energy between different waveguides, and has an input port to receive the optical pulse.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: February 27, 2001
    Assignees: 3M Innovative Properties Company, Massachusetts Institute of Technology
    Inventors: James F. Brennan, III, Dwayne L. LaBrake, Patrick C. Chou, Hermann A. Haus
  • Patent number: 6190981
    Abstract: A method of for fabrication a metal oxide semiconductor transistor is described. A substrate with an isolation structure thereon is provided. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. The polysilicon layer is patterned to form a gate on the gate oxide layer. An offset spacer is formed on the sidewall of the gate. A source/drain extension is formed in the substrate on two sides of the gate by ion implantation. An insulating spacer is formed on the sidewall of the offset spacer. A source/drain region is formed in the substrate by ion implantation using the gate, the offset spacer and the insulating spacer as a mask. Salicide is formed on the gate and on the surface of the source/drain region. After forming the salicide, the offset spacer is removed. After removing the offset spacer, a halo doped region is formed in the substrate below the source/drain extension by ion implantation.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: February 20, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Tony Lin, Jih-Wen Chou
  • Patent number: 6190826
    Abstract: A thermal transfer donor element is provided which comprises a support, a light-to-heat conversion layer, an interlayer, and a thermal transfer layer. When the above donor element is brought into contact with a receptor and imagewise irradiated, an image is obtained which is free from contamination by the light-to-heat conversion layer. The construction and process of this invention is useful in making colored images including applications such as color proofs and color filter elements.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: February 20, 2001
    Assignee: 3M Innovative Properties Company
    Inventors: Jeffrey C. Chang, John S. Staral, William A. Tolbert, Martin B. Wolk, Claire A. Jalbert, Hsin-hsin Chou
  • Patent number: 6190809
    Abstract: A mask combining an alternating phase shift part and an attenuating phase shift part on a single blank and a method of forming said mask. The method involves fewer processing steps, fewer layers of material and is more cost effective than other methods in the current art. A central reason for the simplicity of the method is the use of different intensity levels of E-beam exposure in a single resist layer and achieving phase shifts by transmitting radiation through alternating regions of the same transparent substrate that are etched and not etched.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: February 20, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: San-De Tzu, Ching-Shiun Chiu, Wei-Zen Chou
  • Patent number: 6190757
    Abstract: Coatable thermal mass transfer precursor compositions, suitable for producing thermal mass transfer donor elements, are described, the coatable compositions comprising a polyalkylene binder precursor; an acrylic binder precursor; an effective amount of a pigment to provide the desired color to a thermal mass transfer composition using the coatable composition; and d) a diluent (preferably water) in which the polyalkylene binder precursor, acrylic binder precursor, and pigment are all dispersed therein. Signage articles produced using the donor elements are also described.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: February 20, 2001
    Assignee: 3M Innovative Properties Company
    Inventors: Lisa Flatt Nelson, Hsin-Hsin Chou, Christopher E. Kunze
  • Patent number: 6190982
    Abstract: The present invention relates to a method of fabricating a MOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate. A gate is first formed in a predetermined area on the surface of the semiconductor wafer. A first ion implantation process is then performed to form a doped area on the surface of the silicon substrate adjacent to the gate, the doped area serving as a heavily doped drain (HDD). A uniform and oxygen-free dielectric layer is formed on the surface of the semiconductor wafer that covers the gate. A spacer is formed on each wall of the gate. Finally, a second ion implantation process is performed to form a source and a drain on the surface of the silicon substrate adjacent to the spacer.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: February 20, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Hua-Chou Tseng, Chien-Ting Lin
  • Patent number: 6186719
    Abstract: An improvement in the structure of a capped lock nut includes a nut body made of metal and formed with a shoulder extending upwardly from a top of the nut body and then inwardly to form a flange thereby providing an annular recess between the flange and an upper thread of internal threads of the nut body; a nylon packing ring snugly-fitted within the nut body; and a cap being a hemispherical shell member having an outer diameter which is just equal to an outer diameter of the shoulder of the nut body, whereby the cap can be easily welded to the nut body without causing damage to the nylon packing ring thus strengthening the engagement therebetween and increasing the production rate.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: February 13, 2001
    Inventor: Ming-Chung Chou
  • Patent number: 6187645
    Abstract: A method for manufacturing semiconductor device. The method includes the steps of providing a substrate that has a gate structure thereon, and then forming offset spacers on the sidewalls of the gate structure. Thereafter, a thin oxide annealing operation is conducted, and then a first ion implantation is carried out using the gate structure and the offset spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, secondary spacers are formed on the exterior sidewalls of the offset spacers. Finally, a second ion implantation is carried out using the gate structure, the offset spacers and the secondary spacers as a mask to form source/drain regions within the lightly doped drain regions.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: February 13, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Tony Lin, Coming Chen, Jih-Wen Chou
  • Patent number: 6187652
    Abstract: A method of fabricating a multi-layer interconnected substrate structure. The inventive method includes forming a multi-layer structure from multiple, pre-fabricated power and/or signal substrates which are laminated together. A drill is then used to form a via through the surface of a ring-type pad down to a desired depth in the multi-layer structure. The via hole is cleaned and then filled with a conductive material. The via so formed between two or more substrates is self-aligned by using the ring pad(s). This contributes to an increased signal routing density compared to conventional methods.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: February 13, 2001
    Assignee: Fujitsu Limited
    Inventors: William T. Chou, Solomon I. Beilin, Michael Guang-Tzong Lee, Michael G. Peters, Wen-Chou Vincent Wang
  • Patent number: D438327
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: February 27, 2001
    Assignee: Aloha Housewares Co., Ltd.
    Inventors: Bentley Chelf, Wang Liang Chou
  • Patent number: D438539
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: March 6, 2001
    Assignee: Compal Electronics, Inc.
    Inventors: Shao-Tsu Kung, Ming-Hsun Chou
  • Patent number: D438662
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: March 6, 2001
    Assignee: Aloha Housewares Co., Ltd.
    Inventors: Bentley Chelf, Wang Liang Chou