Patents by Inventor Chou

Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230334053
    Abstract: Systems and methods herein describe a network system for federated searching. The systems and methods receive a search query, transmit the search query to search providers, receive search results corresponding to the search query, extract metadata from each search result, generate matched groupings comprising a first search results that have matching metadata, generate a ranked list of the matched groupings and a plurality of relevance scores, identify a second subset of search results based on the ranked list of matched groupings, and cause display of the second subset of search results on a graphical user interface of a computing device.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 19, 2023
    Inventors: Kapil Gupta, Mengdie Wang, Sivaramakrishnan Natarajan, Houtan Shirani-Mehr, Haonan Duan, Tao Jing, Jesse Chou
  • Publication number: 20230335913
    Abstract: Aspects of the disclosure provide an apparatus for transmitting a circularly polarized signal by linearly polarized antennas. Processing circuitry of the apparatus generates a transmitted baseband signal vector. Based on the transmitted baseband signal vector, power amplifiers (PAs) of the apparatus generates transmitted radio frequency (RF) signals. The transmitted RF signals are received by receiving circuitry of the apparatus to obtain a received baseband signal vector. A controller of the apparatus calibrates the PAs and local oscillator (LO) signals of frequency converters of the apparatus based on the received baseband signal vector. A horizontally polarized antenna and a vertically polarized antenna of the apparatus transmit a circularly polarized signal based on the calibrated PAs and the calibrated LO signals.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 19, 2023
    Applicant: MEDIATEK INC.
    Inventors: Bao-Chi PENG, Shao-Chou HUNG, Chun-Chia CHEN, I-Kang FU, Abdelkader MEDLES, Gilles CHARBIT
  • Publication number: 20230335585
    Abstract: A semiconductor device including a first pair of stacked transistors having a first upper transistor and a first lower transistor, a second pair of stacked transistors comprising a second upper transistor and a second lower transistor, and a first cross-connection between the first upper transistor and the second lower transistor.
    Type: Application
    Filed: April 17, 2022
    Publication date: October 19, 2023
    Inventors: Ruilong Xie, Albert M. Chu, Albert M. Young, Anthony I. Chou, Junli Wang, Brent A. Anderson
  • Publication number: 20230335498
    Abstract: An interconnection structure includes a first conductive feature disposed in a dielectric material, a first etch stop layer disposed over the dielectric material, a first dielectric layer disposed over the first etch stop layer, and a second conductive feature extending through the first dielectric layer and the first etch stop layer and in electrical contact with the first conductive feature. The first etch stop layer includes a boron-based layer, and an oxygen-rich boron-containing layer in contact with the boron-based layer.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 19, 2023
    Inventors: Pei-Yu CHOU, Yu-Lien HUANG, Tze-Liang LEE
  • Patent number: 11791280
    Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a package body and a shield. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a cavity from the second surface extending into the substrate. The first electronic component is disposed on the first surface of the substrate. The second electronic component is disposed within the cavity of the substrate. The package body is disposed on a portion of the first surface of the substrate and covers the first electronic component. The shield is disposed on external surfaces of the package body.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hua Tai, Pai-Chou Liu, Yun-Chih Fei, Wen-Pin Huang, Sheng-Hong Zheng
  • Patent number: 11788997
    Abstract: Embodiments are described of a sensing network including one or more sensor nodes, wherein each of the one or more sensor nodes includes a gas sensor that can measure the presence, concentration, or both, of one or more airborne pollutants in a nodal coverage area surrounding the sensor node. A sensor base that can measure the presence, concentration, or both, of one or more airborne pollutants is positioned in the nodal coverage area of each of the one or more sensor nodes, wherein the sensor base includes a gas sensor with higher accuracy, higher sensitivity, or both, than the gas sensors of the one or more sensor nodes. One or more servers communicatively coupled to the sensor base and the one or more sensors nodes. The sensor base and the sensor nodes can communicate their measurements to the server and the measurements of the sensor base are used by the server as a reference to correct the measurements of the one or more sensor nodes.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: October 17, 2023
    Assignee: Tricorntech Corporation
    Inventor: Tsung-Kuan A. Chou
  • Patent number: 11791357
    Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
  • Patent number: 11789370
    Abstract: A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Dong-Yo Jheng, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu
  • Patent number: 11789296
    Abstract: An optical modulator includes a dielectric layer and a waveguide. The waveguide is disposed on the dielectric layer. The waveguide includes an electrical coupling portion, a slab portion, and an optical coupling portion. The slab portion is directly in contact with both of the electrical coupling portion and the optical coupling portion. The slab portion has a first sub-portion and a second sub-portion connected to the first sub-portion. A top surface of the electrical coupling portion, a top surface of the first sub-portion, and a top surface of the second sub-portion are located at different level heights.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lan-Chou Cho, Chewn-Pu Jou, Feng-Wei Kuo, Huan-Neng Chen, Min-Hsiang Hsu
  • Patent number: 11788129
    Abstract: A GAPDH nucleic acid detection kit includes a primer set for detecting GAPDH nucleic acid. The primer set for detecting GAPDH nucleic acid includes a forward inner primer for GAPDH nucleic acids, a forward outer primer for GAPDH nucleic acids, a backward inner primer for GAPDH nucleic acids and a backward outer primer for GAPDH nucleic acids. The primer set for detecting GAPDH nucleic acid is used in a loop-mediated isothermal amplification (LAMP).
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: October 17, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Min-Yuan Chou, Kuang-Chi Cheng, Ming-Hua Yang, Jiun-Lin Guo
  • Patent number: 11791336
    Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun-Ming Kuo, Pei-Ling Gao, Chen-Hsuan Liao, Hung-Ju Chou, Chih-Chung Chang, Che-Yuan Hsu
  • Patent number: 11791281
    Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 17, 2023
    Assignees: ADVANCED SEMICONDUCTOR ENGINEERING, INC., PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: You-Lung Yen, Pao-Hung Chou, Chun-Hsien Yu
  • Patent number: 11792356
    Abstract: The present technology is directed to determining an accuracy of an infrared (IR) camera, and more particularly, validating a distortion accuracy of an IR camera. The present technology can receive one or more images of a calibration harp captured by the IR camera, wherein the one or more images include a plurality of lines corresponding to a plurality of strings of the calibration harp. The present technology can further determine a degree of distortion of the plurality of lines based on a distortion error coefficient, wherein the distortion error coefficient is computed based on edge points of the plurality of lines on the one or more images.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: October 17, 2023
    Assignee: GM CRUISE HOLDINGS LLC
    Inventors: Yongjun Wang, Marco Antonio Gaxiola Michel, Daniel Chou
  • Patent number: 11792952
    Abstract: An electronic device, including a device body, a case, at least one power supply module, and a power distribution module, is provided. The case is disposed on the device body. The at least one power supply module is disposed in the case. The power distribution module includes a main body, a handle, and an anti-removal frame. The main body is detachably disposed on the device body. The handle is rotatably connected to the main body. The anti-removal frame is slidably disposed in the case. The power supply module is configured to push against the anti-removal frame, so that the anti-removal frame slides toward the handle and restricts the handle from rotating relative to the main body. In addition, a power distribution module configured for the electronic device is also provided.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: October 17, 2023
    Assignee: Wistron Corporation
    Inventors: Zhong-Hui Mao, Hua-Jun Liang, Chih Yao Chou
  • Patent number: 11787681
    Abstract: A damper device for use in an automated beverage preparation apparatus is disclosed. The damper device includes: a damper base having a material entrance hole, a material exit hole, and a material buffer chamber positioned between the material entrance hole and the material exit hole; a diaphragm covered on the material buffer chamber; and a fastening element positioned on the diaphragm and having a hollow portion. When the volume of liquid material within the material buffer chamber exceeds a predetermined amount, the diaphragm deforms to protrude outward, so that a part of the diaphragm enters the hollow portion of the fastening element.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: October 17, 2023
    Assignee: Botrista Technology, Inc.
    Inventors: Wu-Chou Kuo, Yu-Min Lee, Jia-Hui Chen, Yen-Jui Su
  • Patent number: 11788232
    Abstract: A method of making a fabric-creped absorbent cellulosic sheet. The method includes compactively dewatering a papermaking furnish to form a web having a consistency of about thirty percent to about sixty percent, creping the web under pressure in a creping nip between a transfer surface and a structuring fabric, and drying the web to form the absorbent cellulosic sheet. The absorbent sheet has SAT capacities of at least about 9.5 g/g and at least about 500 g/m2. A creping ratio is defined by the speed of the transfer surface relative to the speed of the structuring fabric, and the creping ratio is less than about 25%.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: October 17, 2023
    Assignee: GPCP IP Holdings LLC
    Inventors: Daniel Hue Ming Sze, Xiaolin Fan, Hung-Liang Chou, Taiye Philips Oriaran, Farminder Singh Anand, Dean Joseph Baumgartner, Joseph Henry Miller
  • Patent number: 11790151
    Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
  • Patent number: 11792672
    Abstract: Various embodiments herein define a performance data and measurement job creation solutions for advanced networks including network slicing, based on a service-based framework. The embodiments allow different kinds of consumers to flexibly use performance management services and performance data services, to collect real-time performance data and/or periodical performance data.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: October 17, 2023
    Assignee: Intel Corporation
    Inventors: Yizhi Yao, Joey Chou
  • Patent number: 11787682
    Abstract: A material output volume detecting device for use in an automated beverage preparation apparatus is disclosed. The material output volume detecting device includes: a damper device arranged to operably buffer liquid material flowing therethrough; and a flowmeter arranged to operably measure the flow of liquid material outputted from the damper device. The damper device includes: a damper base having a material entrance hole, a material exit hole, and a material buffer chamber positioned between the material entrance hole and the material exit hole; a diaphragm covered on the material buffer chamber; and a fastening element positioned on the diaphragm and having a hollow portion. When the volume of liquid material within the material buffer chamber exceeds a predetermined amount, the diaphragm deforms to protrude outward, so that a part of the diaphragm enters the hollow portion of the fastening element.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: October 17, 2023
    Assignee: Botrista Technology, Inc.
    Inventors: Wu-Chou Kuo, Yu-Min Lee, Jia-Hui Chen, Yen-Jui Su
  • Patent number: 11791358
    Abstract: A method of forming a semiconductor device includes forming photodiodes extending from a front-side surface of a semiconductor layer into the semiconductor layer; forming transistors on the front-side surface of the semiconductor layer; forming an interconnect structure over the transistors, the interconnect structure comprising an inter-metal dielectric and metal lines in the inter-metal dielectric; etching first regions of a backside surface of the semiconductor layer to form trenches in the semiconductor layer and non-overlapping the photodiodes; after forming the trenches, etching second regions of the backside surface of the semiconductor layer to form pits in the semiconductor layer and overlapping the photodiodes; and depositing a dielectric material in the trenches and the pits.
    Type: Grant
    Filed: August 7, 2021
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee