Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.

Abstract: A method and apparatus for cleaning and sealing components of a display utilizes continuous isolation of the components between the cleaning step and the sealing step. This limits exposure of the components to contaminants and isolates the components from oxidizing agents which can cause an oxide to form on the surface of one or more of the components. In one embodiment, a high vacuum transfer station couples a cleaning station and a sealing station to allow a component to be transferred from the cleaning station to the sealing station without leaving the high vacuum. In another embodiment, the apparatus includes a conveyor transferring the components from the cleaning station at a high vacuum to the sealing station at a similarly high vacuum without exposure to the atmosphere.

Abstract: Phase information is incorporated into a cell-based design methodology. Standard cells have four edges: top, bottom, left, and right. The top and bottom edges have fixed phase shifters placed, e.g. 0. A given cell C will have a phase set created with two versions: 0-180 (left-right) as well as 180-0. Alternatively, the same phase set: 0—0 and 180—180 could be created for a cell. The phase sets are selected based on the ability to phase shift the features within the cell C. By creating a phase set for most of the cells of a cell library, standard cell placement and routing techniques can be used and phase can then be quickly assigned using a simple ripple technique. This ensures a phase compliant design upfront for the standard cell areas.

Abstract: Automated techniques for identifying dummy/main features on a mask layer are provided. In a multiple mask layer technique, the definition of a dummy/main feature can be based on connectivity information or functional association information. In a geometry technique, the definition of a dummy/main feature can be based on a feature size, a feature shape, a pattern of features, or a proximity of a feature to a neighboring feature. In one embodiment, multiple definitions and multiple techniques can be used.

Abstract: Proximity effect correction has become a necessary step in the fabrication of integrated circuit in order to improve the pattern fidelity of current lithography processes. Current methodology is limited by data volume increase and correction inaccuracy due to extrapolation of the correction. The invention describes a methodology based on the interpolation of the correction between selected evaluation points of the target layout. By connecting the correction points this technique also provides a mean of reducing data volume and simplifying the mask writing, inspection and repair processes. The same methodology can be applied to layouts with non-printing assist features, where the correction of the assist features is based on the quality of the image of the main feature. For vector-scan mask write tool the segments interpolating the corrections can be fractured in segments with suitable angles.

Abstract: A mask fabrication and repair technique including multiple exposures is provided. In this multiple exposure technique, the first exposure can define the critical dimensions (CDs) of the shapes for the mask. A subsequent exposure can eliminate isolated defects and significantly reduce the size of defects proximate to the desired shapes on the mask. Because similar processes (i.e. forming, exposing, and developing a photoresist layer) are used for creating and repairing the mask, certain repair-related defects, such as phase and transmission defects, can be minimized. Wafer repair can also be performed using the same multiple exposure technique.

Abstract: Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include selecting from among all edges of all polygons in a proposed layout a subset of edges for which proximity corrections are desirable. The subset of edges includes less than all the edges. Evaluation points are established only for the subset of edges. Corrections are determined for at least portions of the subset of edges based on an analysis performed at the evaluation points. Other techniques include establishing a projection point on a first edge corresponding to the design layout based on whether a vertex of a second edge is within a halo distance. An evaluation point is determined for the first edge based on the projection point and characteristics of the first edge.

Abstract: A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

Abstract: A computer-implemented method for matching parameters of outputs generated by a first and second process. The first process generates a first output having a characteristic measurable by a first parameter, and the second process generates a second output having the characteristic measurable by a second parameter. A computer having a processing unit and memory is provided. The computer generates a first model of the first parameter for the first process and a second model of the second parameter for the second process. The computer generates a first simulated output of the first process using the first model. A correction, which is a function of the second model and which compensates for the effect of the second process on the second parameter, is applied to the first simulated output to obtain a corrected output. The second process is applied to the corrected output to generate with the computer thereby a third output matching the first parameter of the first output.

Abstract: A full phase shifting mask (FPSM) can define substantially all of the features of an integrated circuit using pairs of shifters having opposite phase. In particular, cutting patterns for working with the polysilicon, or gate, layers and active layers of static random access memory (SRAM) cells are considered. To resolve phase conflicts between shifters, one or more cutting patterns can be selected. These cutting patterns include cuts on contact landing pads. This cut simplifies the FPSM layout while ensuring greater critical dimension control of the more important features and reducing mask misalignment sensitivity.

Abstract: Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an approach that uses bins can speed up the clustering process, thereby allowing the phase shifting to be performed in parallel on multiple computers. Additional efficiencies result if identical clusters are identified and processing time saved so that repeated clusters of shapes only undergo the computationally expensive phase shifter placement and assignment process a single time.

Abstract: A lithography reticle advantageously includes “proximity effect halos” around tight tolerance features. During reticle formation, the tight tolerance features and associated halos can be carefully written and inspected to ensure accuracy while the other portions of the reticle can be written/inspected less stringently for efficiency. A system for creating a reticle data file from an IC layout data file can include a processing module and a graphical display. The processing module can read the IC layout data file, identify critical features and define a halo region around each of the critical features. The graphical user interface can facilitate user input and control. The system can be coupled to a remote IC layout database through a LAN or a WAN.

Abstract: Improvements in the fabrication of integrated circuits are driven by the decrease of the size of the features printed on the wafers. Current lithography techniques limits have been extended through the use of phase-shifting masks, off-axis illumination, and proximity effect correction. More recently, liquid immersion lithography has been proposed as a way to extend even further the limits of optical lithography. This invention described a methodology based on contact printing using a projection lens to define the image of the mask onto the wafer. As the imaging is performed in a solid material, larger refractive indices can be obtained and the resolution of the imaging system can be increased.

Abstract: A method of modeling an edge profile for a layer of material is provided. The layer of material can include a resist and/or an etch. In this method, multiple models can be generated, wherein at least two models correspond to different elevations on the wafer. Each model includes an optical model, which has been calibrated using test measurements at the respective elevations. In this manner, an accurate edge profile can be quickly created using the multiple models. Based on the edge profile, layout, mask, and/or process conditions can be modified to improve wafer printing.

Abstract: Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an approach that uses bins can speed up the clustering process, thereby allowing the phase shifting to be performed in parallel on multiple computers. Additional efficiencies result if identical clusters are identified and processing time saved so that repeated clusters of shapes only undergo the computationally expensive phase shifter placement and assignment process a single time.

Abstract: Optimizing printing of an image from an alternating phase shifting mask having a phase shift error is accomplished using off-axis illumination. By simulating the image using varying off-axis illumination parameters, optimized parameters are selected to compensate for the phase shift error. Once the off-axis illumination parameters are optimized, the image is shot. In addition, the method of varying off-axis illumination parameters to compensate for a phase shift error permits an alternating phase shifting mask to be shot at two different wavelengths.

Abstract: Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

Abstract: A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of opposite phase, e.g. 0 and 180 degrees. In one embodiment, a dark field trim mask can be used with the FPSM. The trim mask can include cuts that correspond to cuts on the FPSM. Cuts on the FPSM can be made to resolve phase conflicts between proximate shifters. In one case, exposing two proximate shifters on the FPSM and a corresponding cut on the trim mask can form a feature in the metal layer. The FPSM and/or the trim mask can include proximity corrections to further improve printing resolution.

Abstract: The manufacturing of integrated circuits relies on the use of optical proximity correction (OPC) to correct the printing of the features on the wafer. The data is subsequently fractured to accommodate the format of existing mask writer. The complexity of the correction after OPC can create some issues for vector-scan e-beam mask writing tools as very small slivers are created when the data is converted to the mask write tool format. Moreover the number of shapes created after fracturing is quite large and are not related to some important characteristics of the layout like for example critical areas. A new technique is proposed where the order of the OPC and fracturing steps is reversed. The fracturing step is done first in order to guarantee that no slivers are created and that the number of shapes is minimized. The shapes created can also follow the edges of critical zones so that critical and non-critical edges can be differentiated during the subsequent OPC step.

Abstract: A method of evaluating a stepper process affected by lens aberration is provided. The method includes receiving, from a facilitator responding to a request, a set of optical models including lens aberration information, wherein the lens aberration information is difficult to extract from the optical models. A decision can be made using the set of optical models. The decision could include determining which stepper(s) can be used (or should be avoided) with a mask, a layout, a process, and/or a chemistry. The decision could include ranking a plurality of steppers based on mask data to determine the best stepper (or next best steppers) to use.