Abstract: One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.

Abstract: Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

Abstract: Techniques for forming a design layout with phase-shifted features, such as an integrated circuit layout, include receiving information about a particular phase-shift conflict in a first physical design layout. The information indicates one or more features logically associated with the particular phase-shift conflict. Then the first physical design layout is adjusted based on that information to produce a second design layout. The adjustments rearrange features in a unit of the design layout to collect free space around a selected feature associated with the phase-shift conflict. With these techniques, a unit needing more space for additional shifters can obtain the needed space during the physical design process making the adjustment. The needed space so obtained allows the fabrication design process to avoid or resolve phase conflicts while forming a fabrication layout, such as a mask, for substantiating the design layout in a printed features layer, such as in an actual integrated circuit.

Abstract: To print sub-wavelength features on a wafer, a mask set including a full phase PSM (FPSM) and a corresponding trim mask can be used. Phase assignments on the FPSM can result in some feature definition with the trim mask, particularly in non-critical areas. Unfortunately, this limited feature definition can cause significant critical dimension (CD) variations in these non-critical areas. Undesirable critical dimension (CD) variations can be better controlled, even with substantial mask misalignment, by defining multiple feature edge portions with the trim mask in non-critical areas, such as T-intersections, elbows, and other types of intersecting lines.

Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex “double-T” layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features, including “double-T” features, for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.

Abstract: A lithography reticle advantageously includes “proximity effect halos” around tight tolerance features. During reticle formation, the tight tolerance features and associated halos can be carefully written and inspected to ensure accuracy while the other portions of the reticle can be written/inspected less stringently for efficiency. A system for creating a reticle data file from an IC layout data file can include a processing module and a graphical display. The processing module can read the IC layout data file, identify critical features and define a halo region around each of the critical features. The graphical user interface can facilitate user input and control. The system can be coupled to a remote IC layout database through a LAN or a WAN.

Abstract: A full phase shifting mask (FPSM) can define substantially all of the features of an integrated circuit using pairs of shifters having opposite phase. In particular, cutting patterns for working with the polysilicon, or gate, layers and active layers of static random access memory (SRAM) cells are considered. To resolve phase conflicts between shifters, one or more cutting patterns can be selected. These cutting patterns include cuts on contact landing pads. This cut simplifies the FPSM layout while ensuring greater critical dimension control of the more important features and reducing mask misalignment sensitivity.

Abstract: A system and method for enhancing process latitude (tolerances) in the fabrication of devices and integrated circuits. A measuring point is selected corresponding to a feature of critical dimension. Then the pattern is convolved with the model, and its value and rate of change are calculated over a range of corresponding values of a first process parameter. Next, an optimum threshold having the largest rate of change, or contrast, is selected. Finally, proximity correction is performed using relevant parameters.

Abstract: One embodiment of the invention provides a system that facilitates minimum spacing and/or width control during an optical proximity correction operation for a layout of a mask used in manufacturing an integrated circuit. During operation, the system considers a target edge of a first feature on the mask and then identifies a set of interacting edges in proximity to the target edge. Next, the system performs the optical proximity correction operation, wherein performing the optical proximity correction operation involves applying a first edge bias to the target edge to compensate for optical effects in a resulting image of the target edge. While applying the first edge bias to the target edge, the system allocates an available bias between the first edge bias for the target edge and a second edge bias for at least one edge in the set of interacting edges.

Abstract: A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

Abstract: Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

Abstract: Stepped photoresist profiles provide various methods of forming profiles in an underlying substrate. The stepped photoresist profiles are formed in two layers of photoresist that are disposed over the substrate. The substrate is then etched twice using a respective opening in each photoresist layer to create a stepped profile in the substrate.

Abstract: A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

Abstract: A multi-image reticle used to form integrated circuitry includes a two dimensional array of spaced images arranged in a matrix of controllably spaced rows and columns of images on a single reticle. No rotation of the reticle is required to expose various levels of circuitry on a semiconductor wafer. The wafer is held in a stepper device, which controllably positions the wafer under the desired image of the mask for exposure of a resist on the wafer. A movable aperture controls exposure through a selected image or mask pattern on the reticle. By controlling which image is used, and accurately positioning the wafer via the stepper, multiple images are accurately registered, leading to improvement in dimensions of circuitry and other structures formed on the wafer.

Abstract: A method of evaluating a stepper process affected by lens aberration is provided. The method includes receiving, from a facilitator responding to a request, a set of optical models including lens aberration information, wherein the lens aberration information is difficult to extract from the optical models. A decision can be made using the set of optical models. The decision could include determining which stepper(s) can be used (or should be avoided) with a mask, a layout, a process, and/or a chemistry. The decision could include ranking a plurality of steppers based on mask data to determine the best stepper (or next best steppers) to use.

Abstract: The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.

Abstract: A subresolution grating composed of approximately circular contacts is fabricated around the border of the primary pattern of a photomask. As a result, resolution at the edges of the photomask pattern is improved when the pattern is printed on a wafer surface. In addition, the reduced leakage enables a more efficient use of the glass plate on which the photomask is fabricated as well as a more efficient use of the wafer surface as a result of being able to place patterns closer together.

Abstract: A phase shifting mask can be used to form features on a semiconductor wafer with exposure lights of two different wavelengths. The depth of the phase shifting layer is calculated and fabricated such that it shifts a first exposure light about 180° and a second exposure light about 180°.

Abstract: One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

Abstract: A system and method for optimizing the production of lithography reticles involves identifying “proximity effect halos” around tight tolerance features in an IC layout data file. Features and defects outside the halos will not have a significant effect on the printing of the tight tolerance features. During reticle formation, the tight tolerance features and associated halos can be carefully written and inspected to ensure accuracy while the other portions of the reticle can be written/inspected less stringently for efficiency. The halo width can be determined empirically or can be estimated by process modeling. If an electron beam tool is used to write the reticle, a small spot size can be used to expose the tight tolerance features and the halos, whereas a large spot size can be used to expose the remainder of the reticle. A reticle production system can include a computer to read an IC layout data file, identify tight tolerance features, and define proximity effect halos.