Abstract: Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region.

Abstract: Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region.

Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of assist features and proximity correction features. The method includes applying an adjustment to a phase shift mask pattern including a first and a second phase shift window, and a control chrome with a control width, and/or to a trim mask pattern having a trim shape with a trim width based upon one or both of a rule based correction and a model based correction to improve a match between a resulting exposure pattern and a target feature.

Abstract: When substantially all of a layout for a layer of material in an integrated circuit (IC) is being defined using a phase shifting mask, the complementary mask used to define the remaining features and edges can be improved if some of the cuts on the complementary mask are substantially 180-degrees out of phase with one another. This helps cuts that are close to one another to print better and prevents undesirable deterioration of the features printed using the phase mask. Additionally, (semi-)isolated cuts can be reinforced with assist bars to ensure that the cut clears the unexposed regions left by phase conflicts.

Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

Abstract: One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.

Abstract: The present invention provides a process for performing automatic inspection of advanced design photomasks. In a preferred embodiment, an aerial image of a portion of a photomask is generated. A simulated image corresponding to original pattern data is also generated. The aerial image and simulated image are then compared and discrepancies are detected as possible defects.

Abstract: Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include selecting from among all edges of all polygons in a proposed layout a subset of edges for which proximity corrections are desirable. The subset of edges includes less than all the edges. Evaluation points are established only for the subset of edges. Corrections are determined for at least portions of the subset of edges based on an analysis performed at the evaluation points. Other techniques include establishing a projection point on a first edge corresponding to the design layout based on whether a vertex of a second edge is within a halo distance. An evaluation point is determined for the first edge based on the projection point and characteristics of the first edge.

Abstract: One embodiment of the invention provides a system that performs optical proximity correction in a manner that accounts for properties of a mask writer that generates a mask used in printing an integrated circuit. During operation, the system receives an input layout for the integrated circuit. The system also receives a set of mask writer properties that specify how the mask writer prints features. Next, the system performs an optical proximity correction process on the input layout to produce an output layout that includes a set of optical proximity corrections. This optical proximity correction process accounts for the set of mask writer properties in generating the set of optical proximity corrections, so that the mask writer can accurately produce the set of optical proximity corrections.

Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

Abstract: Shifters on a phase shifting mask (PSM) can be intelligently assigned their corresponding phase. Specifically, the phase of a shifter can be assigned based on simulating the contrast provided by each phase for that shifter. The higher the contrast, the better the lithographic performance of the shifter. Therefore, the phase providing the higher contrast can be selected for that shifter. To facilitate this phase assignment, a pre-shifter can be placed relative to a feature on the layout. The pre-shifter can then be divided into a plurality of shifter tiles for contrast analysis. Model-based data conversion allows for a comprehensive solution including both phase assignment as well as optical proximity correction.

Abstract: Techniques provided for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Included are techniques that correct for proximity effects associated with an edge in a layout corresponding to the design layer.

Abstract: A method extends the use of phase shift techniques to complex layouts, and includes identifying a pattern, and automatically mapping the phase shifting regions for implementation of such features. The pattern includes small features having a dimension smaller than a first particular feature size, and at least one relatively large feature, the at least one relatively large feature and another feature in the pattern having respective sides separated by a narrow space. Phase shift regions are laid out including a first set of phase shift regions to define said small features, and a second set of phase shift regions to assist definition of said side of said relatively large feature. An opaque feature is used to define the relatively large feature, and a phase shift region in the second set is a sub-resolution window inside the perimeter of the opaque feature.

Abstract: One embodiment of the invention provides a system that facilitates minimum spacing and/or width control during an optical proximity correction operation for a layout of a mask used in manufacturing an integrated circuit. During operation, the system considers a target edge of a first feature on the mask and then identifies a set of interacting edges in proximity to the target edge. Next, the system performs the optical proximity correction operation, wherein performing the optical proximity correction operation involves applying a first edge bias to the target edge to compensate for optical effects in a resulting image of the target edge. While applying the first edge bias to the target edge, the system allocates an available bias between the first edge bias for the target edge and a second edge bias for at least one edge in the set of interacting edges.

Abstract: One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout. Next, the system simulates effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. The system then identifies problem areas in the simulated printed image that do not meet a specification. Next, the system moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit, so that a simulated printed image of the new target layout meets the specification.

Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of assist features and proximity correction features. The method includes applying an adjustment to a phase shift mask pattern including a first and a second phase shift window, and a control chrome with a control width, and/or to a trim mask pattern having a trim shape with a trim width based upon one or both of a rule based correction and a model based correction to improve a match between a resulting exposure pattern and a target feature.

Abstract: A mask fabrication and repair technique including multiple exposures is provided. In this multiple exposure technique, the first exposure can define the critical dimensions (CDs) of the shapes for the mask. A subsequent exposure can eliminate isolated defects and significantly reduce the size of defects proximate to the desired shapes on the mask. Because similar processes (i.e. forming, exposing, and developing a photoresist layer) are used for creating and repairing the mask, certain repair-related defects, such as phase and transmission defects, can be minimized. Wafer repair can also be performed using the same multiple exposure technique.

Abstract: Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.

Abstract: One embodiment of the invention provides a system that performs optical proximity correction (OPC) on selected segments on a trim mask used in fabricating an integrated circuit. Upon receiving the trim mask, the system identifies selected segments on the trim mask that do not abut any feature to be printed on the integrated circuit. Next, the system performs a number of OPC operations. The system performs a first OPC operation on the selected segments to correct the selected segments. The system also performs a second OPC operation to correct segments on the trim mask that do abut features to be printed on the integrated circuit. The system additionally performs a third OPC operation on an associated phase shifting mask to correct segments that abut features to be printed on the integrated circuit. (Note that the first, second and third OPC operations can be performed separately or at the same time.