Patents by Inventor Christopher James Kapusta

Christopher James Kapusta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7901970
    Abstract: A micro-electromechanical system (MEMS) based current & magnetic field sensor includes a MEMS-based magnetic field sensing component having a capacitive magneto-MEMS component, a compensator and an output component for sensing magnetic fields and for providing, in response thereto, an indication of the current present in a respective conductor to be measured. In one embodiment, first and second mechanical sense components are electrically conductive and operate to sense a change in a capacitance between the mechanical sense components in response to a mechanical indicator from a magnetic-to-mechanical converter.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: March 8, 2011
    Assignee: General Electric Company
    Inventors: Anis Zribi, Glenn Scott Claydon, Christopher James Kapusta, Laura Jean Meyer, Ertugal Berkcan, Wei-Cheng Tian
  • Publication number: 20100319981
    Abstract: A system and method of forming a patterned conformal structure for an electrical system is disclosed. The conformal structure includes a dielectric coating positioned on an electrical system having circuit components mounted thereon, the dielectric coating shaped to conform to a surface of the electrical system and having a plurality of openings therein positioned over contact pads on the surface of the electrical system. The conformal structure also includes a conductive coating layered on the dielectric coating and on the contact pads such that an electrical connection is formed between the conductive coating and the contact pads. The dielectric coating and the conductive coating have a plurality of overlapping pathway openings formed therethrough to isolate a respective shielding area of the conformal structure over desired circuit components or groups of circuit components.
    Type: Application
    Filed: June 22, 2009
    Publication date: December 23, 2010
    Inventors: Christopher James Kapusta, Donald Paul Cunningham
  • Publication number: 20100244225
    Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.
    Type: Application
    Filed: March 24, 2009
    Publication date: September 30, 2010
    Inventors: James Sabatini, Christopher James Kapusta, Glenn Forman
  • Publication number: 20100244235
    Abstract: An integrated circuit package includes a first dielectric layer comprising a dielectric film having a first side and a second side. The package also includes a die having an active surface affixed to a contact location of the first side of the dielectric film absent a layer of adhesive therebetween that is distinct from a material of the dielectric film. A die stud is affixed to the active surface of the die and extends through the dielectric film to an interconnect location of the second side of the dielectric film, and a via is formed through the dielectric film by the die stud.
    Type: Application
    Filed: May 18, 2009
    Publication date: September 30, 2010
    Inventors: Christopher James Kapusta, James Sabatini
  • Publication number: 20100244226
    Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.
    Type: Application
    Filed: May 8, 2009
    Publication date: September 30, 2010
    Inventors: James Sabatini, Christopher James Kapusta, Glenn Forman
  • Publication number: 20100244240
    Abstract: An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip layer also comprises a first plurality of feed-thru pads coupled to the first side of the first flex layer and a first encapsulant encapsulating the first component, the first encapsulant having a portion thereof removed to form a first plurality of cavities in the first encapsulant and to expose the first plurality of feed-thru pads by way of the first plurality of cavities.
    Type: Application
    Filed: March 24, 2009
    Publication date: September 30, 2010
    Inventors: Christopher James Kapusta, James Sabatini
  • Patent number: 7752751
    Abstract: A system and method for providing shielding to an electrical system is disclosed. A conformal shield is formed by applying a conformal insulating coating to an electrical system. A plurality of openings are formed in the insulating coating at desired locations and a first metallic layer is deposited over the insulating coating and in each of the plurality of openings, the first metallic layer being electrically connected with the circuit board at the desired locations. A second metallic layer is then deposited onto the first metallic layer to increase a thickness of the metallic layers.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: July 13, 2010
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Donald Cunningham, Richard Joseph Saia
  • Patent number: 7741832
    Abstract: A micro-electro-mechanical system (MEMS) current sensor for sensing a magnetic field produced by an electrical current flowing in a conductor includes a first fixed element and a moving element. The moving element is spaced away from the first fixed element and is movable relative to the fixed element responsive to a magnetic field produced by an electrical current flowing in a conductor for providing a mechanical indication of a strength of the magnetic field. The sensor also includes a tunneling current generator for generating a tunneling current between the first fixed element and the moving element and a tunneling current monitor for monitoring a change in the tunneling current responsive to the mechanical indication to provide an indication of a value of the electrical current in the conductor.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: June 22, 2010
    Assignee: General Electric Company
    Inventors: Ertugrul Berkcan, Christopher James Kapusta, Marco Francesco Aimi, Shankar Chandrasekaran, Glenn Scott Claydon
  • Patent number: 7727808
    Abstract: A method for forming an ultra thin die electronic package includes disposing a first polymer film on a first substrate, applying a first adhesive layer to the first polymer film, disposing at least one die on the first adhesive layer, disposing a second polymer film on at least one additional substrate, applying a second adhesive layer to the second polymer film on at least one additional substrate, applying a second adhesive layer to the second polymer film, and attaching the first substrate and the at least one additional substrate via the first adhesive layer and the second adhesive layer such that the at least one die is interspersed between. The method also includes forming multiple vias on a top and/or bottom side of the first and the additional substrate(s), wherein the multiple vias are directly connected to the die, and forming an electrical interconnection between the first substrate, the at least one additional substrate and a die pad of the at least one die.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: June 1, 2010
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Joseph Alfred Iannotti, Kevin Matthew Durocher
  • Publication number: 20100108370
    Abstract: A system and method of forming a patterned conformal structure for an electrical system is disclosed. The conformal structure includes a dielectric coating shaped to conform to a surface of an electrical system, with the dielectric coating having a plurality of openings therein positioned over contact pads on the surface of the electrical system. The conformal structure also includes a patterned conductive coating layered on the dielectric coating and on the contact pads such that an electrical connection is formed between the patterned conductive coating and the contact pads. The patterned conductive coating comprises at least one of an interconnect system, a shielding structure, and a thermal path.
    Type: Application
    Filed: November 3, 2008
    Publication date: May 6, 2010
    Inventors: Christopher James Kapusta, Donald Paul Cunningham
  • Patent number: 7696676
    Abstract: A piezoelectric planar composite apparatus to provide health monitoring of a structure and associated methods are provided. The piezoelectric planar composite apparatus includes a piezoelectric electric material layer, multiple electrodes positioned in electrical contact with the piezoelectric material layer, and multiple sets of electrode interconnect conductors each positioned in electrical contact with a different subset of the electrodes and positioned to form multiple complementary electrode patterns. Each of the complementary electrode patterns is positioned to form an electric field having an electric field axis oriented along a different physical axis from that of an electric field formed by at least one other of the complementary electrode patterns. The interconnect conductors can be distributed over several electrode interconnect conductor carrying layers to enhance formation of the different complementary electrode patterns.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: April 13, 2010
    Assignee: Lockheed Martin Corporation
    Inventors: Ertugrul Berkcan, Emad Andarawis Andarawis, Robert John Wojnarowski, Charles Scott Sealing, Charles Erklin Seeley, Eladio Clemente Delgado, David Cecil Hays, Christopher James Kapusta, Nanette Judith Gruber
  • Publication number: 20090309241
    Abstract: A method for forming an ultra thin die electronic package is provided. The method includes disposing a first polymer film on a first substrate. The method also includes applying a first adhesive layer to the first polymer film on the first substrate. The method further includes disposing at least one die on the first adhesive layer on the first substrate. The method also includes disposing a second polymer film on at least one additional substrate. The method further includes applying a second adhesive layer to the second polymer film on the at least one additional substrate. The method further includes attaching the first substrate and the at least one additional substrate via the first adhesive layer and the second adhesive layer such that the at least one die is interspersed between. The method also includes forming multiple vias on at least one of a top side, and at least one of a bottom side of the first and the at least one additional substrate, wherein the multiple vias are attached to the die.
    Type: Application
    Filed: June 13, 2008
    Publication date: December 17, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Christopher James Kapusta, Joseph Alfred Iannotti, Kevin Matthew Durocher
  • Patent number: 7633667
    Abstract: An integrated electro-optical module apparatus includes in one embodiment an optical modulator configured to modulate an input optical signal coupled thereto; and a control circuit assembly configured to provide electrical control signals to the optical modulator to modulate the input optical signal; wherein the control circuit assembly is attached to the optical modulator in a stacked arrangement.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: December 15, 2009
    Assignee: General Electric Company
    Inventors: Glen Peter Koste, Christopher James Kapusta, Joseph Alfred Iannotti
  • Patent number: 7605466
    Abstract: Multiple microelectromechanical systems (MEMS) on a substrate are capped with a cover using a layer that may function as a bonding agent, separation layer, and hermetic seal. A substrate has a first side with multiple MEMS devices. A cover is formed with through-holes for vias, and with standoff posts for layer registration and separation. An adhesive sheet is patterned with cutouts for the MEMS devices, vias, and standoff posts. The adhesive sheet is tacked to the cover, then placed on the MEMS substrate and heated to bond the layers. The via holes may be metalized with leads for circuit board connection. The MEMS units may be diced from the substrate after sealing, thus protecting them from contaminants.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: October 20, 2009
    Assignee: General Electric Company
    Inventors: Marco Francesco Aimi, Christopher James Kapusta, Arun Virupaksha Gowda, David Cecil Hays, Oliver Charles Boomhower, Glenn Scott Claydon, Joseph Alfred Iannotti, Christopher Fred Keimel
  • Publication number: 20090243081
    Abstract: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Christopher James Kapusta, Donald Cunningham, Richard Joseph Saia, Kevin Durocher, Joseph Iannotti, William Hawkins
  • Publication number: 20090242263
    Abstract: A system and method for providing shielding to an electrical system is disclosed. A conformal shield is formed by applying a conformal insulating coating to an electrical system. A plurality of openings are formed in the insulating coating at desired locations and a first metallic layer is deposited over the insulating coating and in each of the plurality of openings, the first metallic layer being electrically connected with the circuit board at the desired locations. A second metallic layer is then deposited onto the first metallic layer to increase a thickness of the metallic layers.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Christopher James Kapusta, Donald Cunningham, Richard Joseph Saia
  • Publication number: 20090245735
    Abstract: A high temperature optoelectronic device package includes a substrate, an optoelectronic die situated on an upper surface of the substrate, a seal surrounding the optoelectronic die and situated on the upper surface of the substrate and a housing disposed on the seal having a ferrule-seating portion. The housing is disposed on the seal such that a fiber optic center of the ferrule-seating portion is aligned with an active portion of the optoelectronic die. The optoelectronic die is in operative communication with electronic traces of the substrate.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 1, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: David Mulford Shaddock, Christopher James Kapusta, Glen Peter Koste
  • Patent number: 7570133
    Abstract: A true time delay (“TTD”) system with wideband passive amplitude compensation is provided. The TTD system includes an input switch, an output switch, a reference delay line disposed between the input switch and the output switch, and time delay lines disposed between the input switch and the output switch. Each time delay line (“TDL”) has a different line length, and includes a center conductor between two corresponding ground planes. Each center conductor has a width and is separated from the two corresponding ground planes by a gap space. For each TDL, the width of the center conductor is configured such that a loss of the TDL is substantially the same as a loss of every other TDL over a range of operating frequencies. For each TDL, the gap space is configured such that an impedance of the TDL is substantially the same as an impedance of every other TDL.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: August 4, 2009
    Assignee: Lockheed Martin Corporation
    Inventors: William J. Taft, Joseph Alfred Iannotti, Christopher James Kapusta, Anthony W. Jacomb-Hood
  • Publication number: 20090103160
    Abstract: An integrated electro-optical module apparatus includes in one embodiment an optical modulator configured to modulate an input optical signal coupled thereto; and a control circuit assembly configured to provide electrical control signals to the optical modulator to modulate the input optical signal; wherein the control circuit assembly is attached to the optical modulator in a stacked arrangement.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 23, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Glen Peter Koste, Christopher James Kapusta, Joseph Alfred Iannotti
  • Patent number: 7508189
    Abstract: A micro-electromechanical system current and magnetic field sensor is presented. The micro-electromechanical system current and magnetic field sensor is configured to sense a magnetic field produced by a current carrying conductor. The sensor includes a structural component comprising a substrate and a compliant layer, a magnetic-to-mechanical converter coupled to the structural component to provide a mechanical indication of the magnetic field. The sensor further includes a strain responsive component coupled to the structural component to sense the mechanical indication and to provide an indication of the current in the current carrying conductor in response thereto.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: March 24, 2009
    Assignee: General Electric Company
    Inventors: Ertugrul Berkcan, Shankar Chandrasekaran, Christopher James Kapusta, Laura Jean Meyer, Glenn Scott Claydon, Debbie Gahaton Jones, Anis Zribi