Patents by Inventor Chuan Yang

Chuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11594552
    Abstract: Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.
    Type: Grant
    Filed: November 21, 2020
    Date of Patent: February 28, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Bo Xu, Ping Yan, Chuan Yang, Jing Gao, Zongliang Huo, Lu Zhang
  • Patent number: 11587927
    Abstract: A device includes a semiconductor substrate having a first region and a second region. The device further includes a first pair of fin structures within the first region. The device further includes a second pair of fin structures within the second region. A top surface of the semiconductor surface between fin structures within the first pair is higher than a top surface of the semiconductor surface between the first pair and the second pair.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Yu-Kuan Lin
  • Publication number: 20230046028
    Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 16, 2023
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Chih-Hsuan Chen, Kian-Long Lim, Chao-Yuan Chang, Feng-Ming Chang, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20230026103
    Abstract: A cigarette device management system includes an information management module, and a maintenance prediction module, a device state acquisition module and a purchase statistics module which are in communication connection with it. The maintenance prediction module is built by an artificial neural network model and is configured to predict a failure interval. The device state acquisition module acquires a device operating parameter and an operating duration of the device in real time, and compares the device operating parameter with a safety parameter range. In accordance with the system, the maintenance timing of the device can be predicted, the purchase quantity of the spare part and the purchase timing of the spare part also can be predicted.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 26, 2023
    Applicant: Zhangjiakou Cigarette Factory Co., Ltd.
    Inventors: Bo LIU, Aihua ZHANG, Hengzhu SHI, Xiaotang LI, Weidong YAO, Guoping WANG, Zijuan LI, Chuan YANG, Junjie PANG, Peng JI, Mingqi NAN, Zhanbo JIANG, Xiaohua YANG, Jia TIAN, Dongfeng LI, Dong YAN
  • Publication number: 20230027189
    Abstract: A self-adaptive electric toothbrush includes a handle and a brush head. A vibrating motor is arranged in the handle. Bristles are arranged on the brush head. An output shaft of the vibrating motor extends out of the handle and is connected to the brush head through a delay structure. By the delay structure, the brush head remains stationary or the amplitude of the oscillation of the brush head is less than the amplitude of the oscillation of the output shaft after the vibrating motor is activated and before pressure is applied to the bristles. After pressure is applied to the bristles, the amplitude of the oscillation of the brush head is greater than the amplitude of the oscillation before pressure is applied. In the self-adaptive electric toothbrush, before the pressure is applied, the brush head is stationary or the amplitude of oscillation is small.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 26, 2023
    Applicant: CONSTAR MOTION CO.,LTD.
    Inventors: Zhenjian Zhang, Chuansong Qiu, Dong Liu, Chuan Yang, Changjun Wang, Hongping Song
  • Patent number: 11563013
    Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen Su, Chih-Chuan Yang, Shih-Hao Lin, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang
  • Patent number: 11559578
    Abstract: A method for formation of a vaccine comprising combining a cationic polymer adjuvant with an antigen to form first immunoparticles through charge interactions and producing a treatment formulation for the vaccine comprising the first immunoparticles.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: James L. Hedrick, Yi Yan Yang, Ashlynn Lee, Chuan Yang
  • Publication number: 20230012621
    Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.
    Type: Application
    Filed: May 6, 2022
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Chuan YANG, Ruey-Wen CHANG, Feng-Ming CHANG, Kian-Long LIM, Kuo-Hsiu HSU, Lien Jung HUNG, Ping-Wei WANG
  • Patent number: 11552084
    Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping-Wei Wang, Chih-Chuan Yang, Lien Jung Hung, Feng-Ming Chang, Kuo-Hsiu Hsu, Kian-Long Lim, Ruey-Wen Chang
  • Publication number: 20220416046
    Abstract: A method of manufacturing a semiconductor device includes forming a fin, the fin having an epitaxial portion and a base portion protruding from a substrate. Sidewalls of the base portion are tapered with respect to sidewalls of the epitaxial portion. The method also includes depositing a polymeric material on the sidewalls of the epitaxial portion, performing an etching process to modify a profile of the sidewalls of the base portion, such that the sidewalls of the base portion are laterally recessed with a narrowest width of the base portion located under a top surface of the base portion, removing the polymeric material from the sidewalls of the epitaxial portion, depositing an isolation feature on the sidewalls of the base portion, and forming a gate structure engaging the epitaxial portion.
    Type: Application
    Filed: April 15, 2022
    Publication date: December 29, 2022
    Inventors: Shang-Rong Li, Shih-Hao Lin, Wen-Chun Keng, Chih-Chuan Yang, Chih-Hsiang Huang, Ping-Wei Wang
  • Publication number: 20220406372
    Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.
    Type: Application
    Filed: March 18, 2022
    Publication date: December 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao PAO, Kian-Long LIM, Chih-Chuan YANG, Jui-Wen CHANG, Chao-Yuan CHANG, Feng-Ming CHANG, Lien-Jung HUNG, Ping-Wei WANG
  • Patent number: 11525036
    Abstract: Techniques regarding killing of a pathogen with one or more ionene compositions having antimicrobial functionality are provided. For example, one or more embodiments can comprise a method, which can comprise contacting a Mycobacterium tuberculosis microbe with a chemical compound. The chemical compound can comprise an ionene unit. Also, the ionene unit can comprise a cation distributed along a molecular backbone. The ionene unit can have antimicrobial functionality. The method can further comprise electrostatically disrupting a membrane of the Mycobacterium tuberculosis microbe in response to the contacting.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: December 13, 2022
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Mareva B. Fevre, James L. Hedrick, Nathaniel H. Park, Victoria A. Piunova, Pang Kern Jeremy Tan, Chuan Yang, Yi Yan Yang
  • Publication number: 20220375944
    Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 24, 2022
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Hsin-Wen Su, Kian-Long Lim, Chien-Chih Lin
  • Patent number: 11508738
    Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Hsin-Wen Su, Kian-Long Lim, Chien-Chih Lin
  • Publication number: 20220367481
    Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu, Feng-Ming Chang, Wen-Chun Keng, Lien Jung Hung
  • Publication number: 20220367482
    Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 17, 2022
    Inventors: Wen-Chun Keng, Kuo-Hsiu Hsu, Chih-Chuan Yang, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20220367459
    Abstract: A method includes forming an anti-punch-through layer over a first region and a second region of a substrate, forming a semiconductor layer over the anti-punch-through layer, patterning the semiconductor layer and the anti-punch-through layer to form a first plurality of fins over the first region and a second plurality of fins over the second region, and forming a patterned resist layer over the first plurality of fins and the second plurality of fins. The method also includes recessing a portion of the substrate between the first plurality of fins and the second plurality of fins in an etching process through openings of the patterned resist layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Chih-Chuan Yang, Yu-Kuan Lin
  • Publication number: 20220367728
    Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
  • Publication number: 20220367725
    Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Inventors: Shih-Hao LIN, Chong-De LIEN, Chih-Chuan YANG, Chih-Yu HSU, Ming-Shuan LI, Hsin-Wen SU
  • Patent number: D974866
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: January 10, 2023
    Inventor: Te-Chuan Yang