Patents by Inventor Chul Woo Park

Chul Woo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nonvolatile memory device with a clamping voltage generation circuit for compensating the variations in memory cell parameters
    Patent number: 8654595
    Abstract: A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Kyung Kim, Hong-Sun Hwang, Chul-Woo Park, Sang-Beom Kang, Hyung-Rok Oh
  • Semiconductor memory device having a hierarchical bit line scheme
    Patent number: 8638621
    Abstract: A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-pil Son, Chul-woo Park, Young-hyun Jun, Hong-sun Hwang, Hak-soo Yu
  • SEMICONDUCTOR MEMORY DEVICE HAVING RESISTIVE MEMORY CELLS AND METHOD OF TESTING THE SAME
    Publication number: 20140022836
    Abstract: A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. The MTJ element includes a free layer, a barrier layer and a pinned layer. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 23, 2014
    Inventors: Hye-Jin KIM, Hyung-Rok OH, Dong-Seok KANG, Dong-Hyun SOHN, Sang-Beom KANG, Chul-Woo PARK, Yun-Sang LEE
  • APPARATUS FOR MEASURING FLOATING MICROORGANISMS IN A GAS PHASE IN REAL TIME USING A SYSTEM FOR DISSOLVING MICROORGANISMS AND ATP ILLUMINATION, AND METHOD FOR DETECTING SAME
    Publication number: 20140017723
    Abstract: The present invention relates to an apparatus for measuring floating microorganisms in a gas phase in real time using a system for dissolving microorganisms and adenosine triphosphate (ATP) illumination, and to a method for detecting same. The measuring apparatus includes a particle classifying apparatus for collecting floating microorganisms and being coated by an ATP reaction illuminating agent; a system for dissolving microorganisms for dissolving the microorganisms and extracting ATP; and a light receiving device for detecting light generated from the reaction of the extracted ATP by the system and the ATP reaction illuminating agent coated on the particle classifying apparatus. According to the detection method using ATP organism illumination, the floating microorganisms in the gas phase can be readily detected and the detection can be automatically conducted in real time without manual labor.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 16, 2014
    Applicant: INDUSTRY-ACADEMIC COOPERATION FOUNDATION YONSEI UNIVERSITY
    Inventors: Jung Ho Hwang, Chul Woo Park, Jae Hong Park, Yang Seon Kim
  • MAGNETIC RANDOM ACCESS MEMORY
    Publication number: 20140016404
    Abstract: A magnetic memory device such as a magnetic random access memory (MRAM), and a memory module and a memory system on which the magnetic memory device is mounted are disclosed. The MRAM includes magnetic memory cells each of which varies between at least two states according to a magnetization direction and an interface unit that provides various interface functions. The memory module includes a module board and at least one MRAM chip mounted on the module board, and further includes a buffer chip that manages an operation of the at least one MRAM chip. The memory system includes the MRAM and a memory controller that communicates with the MRAM, and may communicate an electric-to-optical conversion signal or an optical-to-electric conversion signal by using an optical link that is connected between the MRAM and the memory controller.
    Type: Application
    Filed: July 9, 2013
    Publication date: January 16, 2014
    Inventors: Chan-kyung Kim, Soo-ho Cha, Dong-seok Kang, Chul-woo Park, Dong-hyun Sohn, Yun-sang Lee, Hye-jin Kim
  • SEMICONDUCTOR MEMORY DEVICE HAVING STACKED STRUCTURE INCLUDING RESISTOR-SWITCHED BASED LOGIC CIRCUIT AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20140008598
    Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.
    Type: Application
    Filed: September 4, 2013
    Publication date: January 9, 2014
    Inventors: In-gyu Baek, Hong-sun Hwang, Hak-soo Yu, Chul-woo Park
  • MEMORY DEVICES WITH SELECTIVE ERROR CORRECTION CODE
    Publication number: 20140013183
    Abstract: An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells.
    Type: Application
    Filed: June 11, 2013
    Publication date: January 9, 2014
    Inventors: Young-Soo SOHN, Chul-Woo PARK, Jong-Pil SON, Jung-bae LEE
  • Stacked memory devices
    Patent number: 8611121
    Abstract: A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: December 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-eon Ahn, Ho-jung Kim, Chul-woo Park, Sang-beom Kang, Hyun-ho Choi
  • SEMICONDUCTOR MEMORY DEVICES AND RELATED METHODS OF OPERATION
    Publication number: 20130322162
    Abstract: A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 5, 2013
    Inventors: YUN-SANG LEE, DONG-SEOK KANG, SANG-BEOM KANG, CHAN-KYUNG KIM, CHUL-WOO PARK, DONG-HYUN SOHN, HYUNG-ROK OH
  • MAGNETIC RANDOM ACCESS MEMORY
    Publication number: 20130311717
    Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.
    Type: Application
    Filed: February 15, 2013
    Publication date: November 21, 2013
    Applicants: GLOBIT CO., LTD., DIGITAL MEDIA RESEARCH INSTITUTE, INC.
    Inventors: Chan-kyung Kim, Dong-seok Kang, Hye-jin Kim, Chul-woo Park, Dong-hyun Sohn, Yun-sang Lee, Sang-beom Kang, Hyung-rok Oh, Soo-ho Cha
  • Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
    Patent number: 8588017
    Abstract: A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-woo Park, Young-hyun Jun, Joo-sun Choi, Hong-sun Hwang
  • Systems, devices and methods using redundant error correction code bit storage
    Patent number: 8589767
    Abstract: A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: November 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Beom Kang, Chul Woo Park, Hyun Ho Choi, Ho Jung Kim
  • MEMORY DEVICES AND MEMORY CONTROLLERS
    Publication number: 20130279283
    Abstract: A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals.
    Type: Application
    Filed: January 3, 2013
    Publication date: October 24, 2013
    Inventors: Eun-Sung SEO, Chul-Woo PARK, Hong-Sun HWANG
  • VOLATILE MEMORY DEVICE AND A MEMORY CONTROLLER
    Publication number: 20130282973
    Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.
    Type: Application
    Filed: December 19, 2012
    Publication date: October 24, 2013
    Inventors: Sang-Yun KIM, Jong-Pil SON, Su-A KIM, Chul-Woo PARK, Hong-Sun HWANG
  • Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same
    Patent number: 8553445
    Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-gyu Baek, Hong-sun Hwang, Hak-soo Yu, Chul-woo Park
  • Semiconductor memory device for data sensing
    Patent number: 8553484
    Abstract: A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sua Kim, Chul-Woo Park, Hong-Sun Hwang, Hak-Soo Yu
  • STACKED MEMORY DEVICE AND METHOD OF FABRICATING SAME
    Publication number: 20130237019
    Abstract: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.
    Type: Application
    Filed: April 17, 2013
    Publication date: September 12, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Woo PARK, Hong-Sun HWANG, In-Gyu BAEK, Dong-Hyun SOHN
  • MEMORY DEVICE, METHOD OF PERFORMING READ OR WRITE OPERATION AND MEMORY SYSTEM INCLUDING THE SAME
    Publication number: 20130148429
    Abstract: Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.
    Type: Application
    Filed: December 4, 2012
    Publication date: June 13, 2013
    Inventors: Chan-Kyung Kim, Yun-Sang Lee, Chul-Woo Park, Hong-Sun Hwang
  • Stacked memory device and method of fabricating same
    Patent number: 8441852
    Abstract: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: May 14, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-Woo Park, Hong-Sun Hwang, In-Gyu Baek, Dong-Hyun Sohn
  • Semiconductor device, semiconductor system including the same, and voltage supply method of semiconductor device
    Patent number: 8422328
    Abstract: A semiconductor device, a semiconductor system including the same, and a voltage supply method of the semiconductor device are provided. The semiconductor device includes at least two semiconductor memory devices and a voltage supply controller configured to selectively supply a voltage to each of the at least two semiconductor memory devices.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: April 16, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Jung Kim, Chul Woo Park, Sang Beom Kang, Jung Min Lee, Hyun Ho Choi