Patents by Inventor Chun-An Hsieh

Chun-An Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10803280
    Abstract: A fingerprint identification device includes a substrate, a piezoelectric layer, a conductive layer, and a planar layer. The piezoelectric layer is disposed on the substrate. The conductive layer is disposed on the piezoelectric layer, and the conductive layer has a rugged microstructure on an upper surface of the conductive layer. The planar layer is disposed on the conductive layer, and a bottom of the planar layer fills the rugged microstructure of the conductive layer.
    Type: Grant
    Filed: October 21, 2018
    Date of Patent: October 13, 2020
    Assignee: RECO TECHNOLOGY (CHENGDU) CO., LTD.
    Inventors: Pei-Chun Hsieh, Hung-Chieh Lu
  • Patent number: 10795447
    Abstract: A keyswitch with adjustable tactile feedback is adjusted by an adjusting method. The keyswitch includes a baseplate, an upper housing, an upper bushing component, a lower bushing component, a keycap and a recovering component. The baseplate has an electrode module, the upper housing is disposed on the baseplate, the upper bushing component is movably disposed on the upper housing, the lower bushing component is movably located between the baseplate and the upper housing, and the keycap is connected to a connecting portion of the upper bushing component. The lower bushing component can rotate relative to the baseplate to switch between a first position and a second position. The lower bushing component has a first lateral surface and a second lateral surface with different shapes. The recovering component is disposed between the baseplate and the lower bushing component to upwardly push the lower bushing component.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: October 6, 2020
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Chen Yang, Chia-Hung Liu, Yung-Chih Wang, Yu-Chun Hsieh
  • Publication number: 20200303557
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate. The tunneling oxide layer is formed on a substrate. The floating gate is formed on the tunneling oxide layer, and includes a first polysilicon layer, a second polysilicon layer, and a nitrogen dopant. A grain of the first polysilicon layer has a first grain size, and a grain of the second polysilicon layer has a second grain size that is greater than the first grain size. The nitrogen dopant is formed in interstices between the grains of the first polysilicon layer. The dielectric layer includes a first nitride film, an oxide layer, a nitride layer, and an oxide layer conformally formed on the floating gate. The control gate is formed on the dielectric layer.
    Type: Application
    Filed: June 10, 2020
    Publication date: September 24, 2020
    Inventors: Chu-Chun HSIEH, Tse-Mian KUO
  • Publication number: 20200287508
    Abstract: An amplifier circuit is provided, which includes an input stage circuit, at least one impedance component and a current supply circuit, where the input stage circuit is coupled between at least one input terminal of the amplifier circuit and at least one output terminal of the amplifier circuit, the impedance component is coupled between a first reference voltage and the output terminal, and the current supply circuit is coupled between a second reference voltage and the output terminal. The input stage circuit is arranged to generate a signal current in response to an input signal on the input terminal, and the current supply circuit is arranged to provide at least one adjustment current. In addition, a common mode voltage level of an output signal on the output terminal is controlled by the adjustment current, to allow the amplifier circuit to perform low voltage operations.
    Type: Application
    Filed: July 23, 2019
    Publication date: September 10, 2020
    Inventors: Yu-Ting Chung, Shawn Min, Yi-Chun Hsieh
  • Patent number: 10768477
    Abstract: Provided is a backlight module including a light guide plate, a light source and a light conversion layer. The light source is disposed at one side of the light guide plate. The light conversion layer is disposed over the light guide plate. The light conversion layer includes an optical composite material including 0.1 wt % to 15 wt % of a luminescent material and 85 wt % to 99.9 wt % of an acrylate-based polymer. The acrylate-based polymer is prepared from precursors including 5 wt % to 30 wt % of a surfactant having a thiol group.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: September 8, 2020
    Assignee: Unique Materials Co., Ltd.
    Inventors: Huan-Wei Tseng, Chia-Chun Hsieh, Chun-Wei Chou
  • Patent number: 10771198
    Abstract: The described technology is generally directed towards adaptively selecting a repetition level in wireless communications, based on events to improve coverage range via the repetition level while not unnecessarily reducing throughput. One such event can include a current signal-to-noise-ratio, e.g., as reported in a channel quality indicator report from a user equipment. Another such event can comprise a number of consecutive hybrid automatic repeat request acknowledgments or negative acknowledgments (HARQ ACKS/NACKS), in which consecutive ACKs tend to indicate good signal quality, while consecutive NACKs tend to indicate poor signal quality. A combination of channel quality indicator-based adaptive repetition level and HARQ ACK/NACK-based adaptive repetition level can be employed.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 8, 2020
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Yupeng Jia, Darwin Parra, Prabhakara Aithal, Ping-Chun Hsieh
  • Publication number: 20200244261
    Abstract: A keyswitch includes a circuit board, a bottom board abutting against the circuit board, a cap, a light receiver and a light emitter disposed on the circuit board and opposite to each other, a base disposed on the circuit board, a cover disposed on the base, a first elastic member disposed through the cover and the base, a support device, and a second elastic member fixed to the base and having a flexible rod. The support device is movably connected to the cap and bottom board and has a sheet structure. When the cap is pressed, the sheet structure blocks light transmission between the light emitter and the light receiver to generate a triggering signal. When the cap is pressed to make the flexible rod deform downward with the sheet structure and then cross the sheet structure, the flexible rod is released to collide with the cover to make sound.
    Type: Application
    Filed: January 20, 2020
    Publication date: July 30, 2020
    Inventors: Yu-Chun Hsieh, Chen Yang, Chia-Hung Liu
  • Publication number: 20200232712
    Abstract: A heat dissipation device includes a main body and at least one heat conduction member. The main body has a top face. A periphery of the top face has a connection section. One end of the heat conduction member is correspondingly in contact and connection with the top face or the connection section. By means of the structure design of the present invention, the horizontal heat dissipation effect is greatly enhanced and the heat dissipation effect of the entire heat dissipation device is greatly enhanced.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 23, 2020
    Inventor: Kuo-Chun Hsieh
  • Patent number: 10720533
    Abstract: A non-volatile memory device and its manufacturing method are provided. The non-volatile memory device includes a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate. The tunneling oxide layer is formed on a substrate. The floating gate is formed on the tunneling oxide layer, and includes a first polysilicon layer, a second polysilicon layer, and a nitrogen dopant. A grain of the first polysilicon layer has a first grain size, and a grain of the second polysilicon layer has a second grain size that is greater than the first grain size. The nitrogen dopant is formed in interstices between the grains of the first polysilicon layer. The dielectric layer includes a first nitride film, an oxide layer, a nitride layer, and an oxide layer conformally formed on the floating gate. The control gate is formed on the dielectric layer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 21, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chu-Chun Hsieh, Tse-Mian Kuo
  • Patent number: 10721102
    Abstract: A communication apparatus includes an input terminal, an output terminal, and an interference reduction circuit. The interference reduction circuit is coupled between the input terminal and the output terminal. The interference reduction circuit receives a time-varying data signal. The interference reduction circuit acquires first partial data from the data signal at a first time, and generates a first level-shifted result and a second level-shifted result according to the first partial data. The interference reduction circuit is further configured to acquire second partial data from the data signal at a second time. The interference reduction circuit selects one of the first level-shifted result and the second level-shifted result as a selected result according to the second partial data, and sends the selected result to the output terminal.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 21, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kai-An Hsieh, Yi-Chun Hsieh
  • Patent number: 10715359
    Abstract: The present invention provides a decision feedback equalizer including a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit generates a first set signal and a first reset signal according to an input signal, a second set signal and a second reset signal, and the first latch circuit generates a first digital signal according to the first set signal and the first reset signal. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit generates the second set signal and the second reset signal according to the input signal, the first set signal and the first reset signal, and the second latch circuit generates a second digital signal according to the second set signal and the second reset signal.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: July 14, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hsi-En Liu, Shawn Min, Yi-Chun Hsieh
  • Publication number: 20200217593
    Abstract: A flat-plate heat pipe structure includes a main body. The main body has a first board body, a second board body, a first capillary structure and a working fluid. The first and second board bodies are overlapped and mated with each other. The first capillary structure is disposed between the first and second board bodies. The first capillary structure and the first and second board bodies together define at least one vapor passage. Accordingly, when the flat-plate heat pipe is thinned, the flat-plate heat pipe still keeps having a vapor passage, whereby the vapor-liquid circulation efficiency of the flat-plate heat pipe will not be deteriorated due to thinning.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 9, 2020
    Inventor: Kuo-Chun Hsieh
  • Publication number: 20200211979
    Abstract: The present disclosure relates to a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate including a first surface and a conductive trace extending over the substrate; a die disposed over the first surface of the substrate; a molding disposed over the first surface of the substrate and covering the die; and a metallic layer surrounding the molding and the substrate, wherein the metallic layer is electrically connected to at least a portion of the conductive trace exposed through the substrate.
    Type: Application
    Filed: April 17, 2019
    Publication date: July 2, 2020
    Inventors: Chang-Chun HSIEH, Wu-Der YANG, Ching-Feng CHEN
  • Publication number: 20200196482
    Abstract: A heat dissipation unit includes a main body having an upper surface and a lower surface and at least one heat conduction member having a heat absorption face and a heat conduction face. The heat conduction face of the heat conduction member is disposed under the lower surface of the main body.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Kuei-Feng Chiang, Kuo-Chun Hsieh
  • Publication number: 20200191496
    Abstract: A manufacturing method of heat dissipation unit includes steps of: providing a mold having an upper mold section and a lower mold section, the lower mold section being formed with a receiving depression and at least one sink; providing an upper plate, a lower plate, a capillary structure and at least one heat conduction member, the heat conduction member being positioned in the sink, the lower plate, the capillary structure and the upper plate being sequentially positioned in the receiving depression, then the heat conduction member, the lower plate, the capillary structure and the upper plate being thermally pressed and connected with each other by means of the upper and lower mold sections; and integrally connecting the heat conduction member with the lower plate when the upper and lower plates are thermally pressed and connected to form the plate body by means of the upper and lower mold sections.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Kuei-Feng Chiang, Kuo-Chun Hsieh
  • Publication number: 20200183240
    Abstract: A device substrate including a substrate, first fan-out lines, second fan-out lines, third fan-out lines, touch electrode lines, and active devices is provided. The substrate includes an active area and a peripheral area connected with the active area. The first fan-out lines, the second fan-out lines, and the third fan-out lines are disposed on the peripheral area. Each of the second fan-out lines is overlapped with one corresponding first fan-out line. The second fan-out lines and the first fan-out lines belong to different conductive layers. Each of the third fan-out lines is disposed between two corresponding first fan-out lines. The third fan-out lines and the first fan-out lines belong to the same conductive layer. The touch electrode lines are electrically connected with the third fan-out lines. The active devices are disposed on the active area and electrically connected with the first fan-out lines and the second fan-out lines.
    Type: Application
    Filed: October 29, 2019
    Publication date: June 11, 2020
    Applicant: Au Optronics Corporation
    Inventors: Hsiu-Chun Hsieh, Yi-Wei Chen
  • Publication number: 20200141096
    Abstract: A floor faucet structure contains: a body, an adjustable fitting sleeve, a fixing seat, and a connection sleeve. The body includes a positioning disc, a cold-water inlet tube, and a hot-water inlet. Each of the cold-water inlet tube and the hot-water inlet tube has a respective one rotation members and a respective one connector. The respective one rotation member has a longitudinal extension, a horizontal extension, and a first conduit. The respective one connector includes a first connecting section, a second connecting section, a second conduit, at least one stop ring, a first external threaded section, and a second external threaded section. The adjustable fitting sleeve includes a first coupling portion, the fixing seat includes a circular groove, multiple retaining ribs. The connection sleeve includes a second coupling portion, a cylindrical fence, and multiple locking ribs.
    Type: Application
    Filed: January 8, 2020
    Publication date: May 7, 2020
    Inventors: Ming-Chun Hsieh, Chia-Yi Hsieh
  • Patent number: 10637470
    Abstract: An optical keyswitch includes a casing having a movable portion, a shaft movably disposed on the casing, a resilient member accommodated in the casing, and a switch module including a circuit board, an emitter, and a receiver. The emitter emits an optical signal along an optical path to the receiver. When the shaft is at a non-pressed position, the movable portion has a first spatial relation with the optical path, and the receiver receives the optical signal of a first intensity. When the shaft moves, in response to a pressing force, to a pressed position, the shaft compresses the resilient member and pushes the movable portion to move, so the movable portion no longer has the first spatial relation with the optical path, the optical signal received by the receiver has a second intensity different from the first intensity, and the switch module is triggered to generate a triggering signal.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: April 28, 2020
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Yung-Chih Wang, Yu-Chun Hsieh, Chen Yang, Chia-Hung Liu
  • Publication number: 20200122533
    Abstract: The present invention provides an unique ID electronic (UM) tag for a tire, which is suitable to be mounted on a surface of tire or embedded in a tire, comprising: a tag unit; a pliable protective layer; and a vuicanizable bonding layer. The pliable protective layer provided on two opposite sides of the tag unit. The vulcanizable bonding layer provided on one or each of the two opposite sides of the pliable protective layer to bond the UID tag tightly to the tire during a vulcanization process. Further, the tag unit comprises a circuit substrate provided with an antenna circuit, and an integrated circuit (IC) chip electrically connected to the antenna circuit.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 23, 2020
    Inventors: PI SUNG SU, HSIN CHENG PAO, YUN-DA JUNG, CHI CHUN HSIEH
  • Publication number: 20200126787
    Abstract: A method for lithography patterning includes depositing a target layer over a substrate, the target layer including an inorganic material; implanting ions into the target layer, resulting in an ion-implanted target layer; forming a photoresist layer directly over the ion-implanted target layer; and exposing the photoresist layer to radiation in a photolithography process. The ion-implanted target layer reduces reflection of the radiation back to the photoresist layer during the photolithography process.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Cheng-Han Yang, Tsung-Han Wu, Chih-Wei Chang, Hsin-mei Lin, I-Chun Hsieh, Hsi-Yen Chang