Patents by Inventor Chun-An Lu

Chun-An Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230275247
    Abstract: Provided is an aqueous redox flow battery comprising a positive electrode, a negative electrode, a posolyte chamber containing a posolyte, a negolyte chamber containing a polyoxometalate as a negolyte, and a separator disposed between the posolyte chamber and the negolyte chamber, wherein the polyoxometalate has a conductivity of 65 mS cm?1 or more at ?20° C., and the aqueous redox flow battery has a power density of 250 mW cm?2 or more at ?20° C.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Inventors: Yi-Chun LU, Fei AI
  • Patent number: 11733790
    Abstract: A ring input device, and more particularly to pressure-sensitive input mechanisms within the ring input device that detect pressure to initiate an operation, is disclosed. Because finger rings are often small and routinely worn, electronic finger rings can be employed as unobtrusive communication devices that are readily available to communicate wirelessly with other devices capable of receiving those communications. Ring input devices according to examples of the disclosure can detect press inputs on its band to generate inputs that can then be wirelessly communicated to companion devices.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: August 22, 2023
    Assignee: Apple Inc.
    Inventors: Michael Beyhs, Richard G. Huizar, Filip Ilievski, Jean Hsiang-Chun Lu, Thayne M. Miller
  • Patent number: 11715706
    Abstract: The present application discloses a semiconductor chip, a semiconductor device and an electrostatic discharge (ESD) protection method for a semiconductor device. The semiconductor chip includes an electrical contact, an application circuit, and an ESD protection unit. The application circuit performs operations according to a one signal received by the electrical contact. The ESD protection unit is coupled to the electrical contact. The capacitance of the ESD protection unit is adjustable.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: August 1, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Lu Lee
  • Publication number: 20230240087
    Abstract: An IC package includes a substrate, a first monolithic die, a second monolithic die and a third monolithic die. A processing unit circuit is formed in the first monolithic die. A plurality of SRAM arrays are formed in the second monolithic die, wherein the plurality of SRAM arrays include at least 5-20 G Bytes. A plurality of DRAM arrays are formed in the third monolithic die, wherein the plurality of DRAM arrays include at least 64-512 G Bytes. The first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate. The third monolithic die is electrically connected to the first monolithic die through the second monolithic die.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 27, 2023
    Applicant: Invention And Collaboration Laboratory Pte. Ltd.
    Inventor: Chao-Chun LU
  • Publication number: 20230225659
    Abstract: A wearable electronic device includes a housing, and an electrode carrier attached to the housing and having a nonplanar surface. The wearable electronic device includes a set of electrodes, including electrodes positioned at different locations on the nonplanar surface. The wearable electronic device includes a sensor circuit and a switching circuit. The switching circuit is operable to electrically connect a number of different subsets of one or more electrodes in the set of electrodes to the sensor circuit.
    Type: Application
    Filed: January 9, 2023
    Publication date: July 20, 2023
    Inventors: Erdrin Azemi, Ali Moin, Anuranjini Pragada, Jean Hsiang-Chun Lu, Victoria M. Powell, Juri Minxha, Steven P. Hotelling
  • Patent number: 11699900
    Abstract: The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: July 11, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Lu Lee
  • Publication number: 20230215416
    Abstract: A biquad hybrid active noise cancellation (ANC) device includes a reference microphone (MIC), an error MiC, a speaker, and a controller. The controller is connected to the reference MiC, the error MiC, and the speaker, wherein the controller includes a feedforward biquad ANC filter, a feedback biquad ANC filter, and a mixer, the feedforward biquad ANC filter processes reference noise to generate a feedforward noise control signal, the feedback biquad ANC filter processes residual noise received by the error MiC to generate a feedback noise control signal, and the feedforward noise control signal generated by the feedforward biquad ANC filter and the feedback noise control signal generated by the feedback biquad ANC filter are added by the mixer and transmits to the speaker for playing.
    Type: Application
    Filed: January 5, 2022
    Publication date: July 6, 2023
    Applicant: BlueX Microelectronics ( Hefei ) Co., Ltd.
    Inventors: Hao-Ming Chen, Yi-Chun Lu, HONGYU LI
  • Publication number: 20230214399
    Abstract: The present invention provides a patent search system, comprising: a database storing a plurality of first patent document data items; and a server accessing the database, the server receiving a first search criterion instruction and then retrieving a plurality of second patent document data items from the plurality of first patent document data items based on the first search criterion instruction, wherein the server receives a first selection instruction associated with a first selected patent document data item in the plurality of second patent document data items, obtains a first patent classification code data item from the first selected patent document data item based on the first selection instruction, and generates a second search criterion instruction based on at least the first search criterion instruction and the first patent classification code data item, the second search criterion instruction including the first patent classification code data item, wherein the server retrieves a plurality of t
    Type: Application
    Filed: June 15, 2022
    Publication date: July 6, 2023
    Applicant: KKLAB TECHNOLOGIES PTE. LTD.
    Inventors: Shih Chun Lu, Shih Hung Lin, Sheng Fu Lin
  • Patent number: 11695003
    Abstract: The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: July 4, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Lu Lee
  • Publication number: 20230207645
    Abstract: A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.
    Type: Application
    Filed: February 21, 2023
    Publication date: June 29, 2023
    Applicants: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.
    Inventors: Chao-Chun Lu, Li-Ping Huang
  • Publication number: 20230202855
    Abstract: The present disclosure discloses a method for strengthening a biological manganese oxidation using a magnetic field and use thereof. The method includes steps of inoculating a manganese-oxidizing microorganism into a culture medium containing Mn2+, performing magnetization treatment in a culture process, and then collecting a biogenic manganese oxide. The method includes steps of performing a primary magnetic field treatment at a magnetic field intensity of 0.2-50 mT for 1-5 h when culturing is performed for 6-12 h, continuing culturing after the primary magnetization treatment, and performing magnetization treatment once every other 24 h for culture time of 72 h. A magnetic field is applied to accelerate an oxidation rate of a manganese-oxidizing microorganism to Mn2+and a biological manganese oxidation rate is respectively improved by 36.4% and 23.8% under an action of an alternating magnetic field or a constant magnetic field within 72 h.
    Type: Application
    Filed: March 6, 2023
    Publication date: June 29, 2023
    Applicant: TONGJI UNIVERSITY
    Inventors: Mei Wang, Zuxin Xu, Bin Dong, Mengke CUI, Sisi Chen, Yifan ZENG, Chun LU
  • Publication number: 20230200040
    Abstract: An integration system includes a first monolithic die and a second monolithic die. The first monolithic die has a processing unit circuit formed therein; and the second monolithic die has a plurality of SRAM arrays formed therein. Wherein the second monolithic die comprises at least 2G Bytes; and the first monolithic die is electrically connected to the second monolithic die.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 22, 2023
    Applicant: Invention And Collaboration Laboratory Pte. Ltd.
    Inventor: Chao-Chun LU
  • Publication number: 20230176060
    Abstract: Biomarkers for prognosis of tumours, in hepatocellular carcinoma and other cancers. Measurement of biomarkers for prescription of anticancer immunotherapy targeted against ICOS+ regulatory T cells (TReg), e.g., selecting patients for treatment with an anti-ICOS antibody. Biomarkers comprising: (i) ratio of the number of ICOS FOXP3 double positive cells within a defined radius of influence around ICOS single positive cells to the total number of ICOS single positive cells, (ii) mean distance between each ICOS positive FOXP3 negative cell and its nearest ICOS FOXP3 double positive cell, (iii) proportion of FOXP3 positive cells which are ICOS positive, and (iv) density of ICOS positive cells.
    Type: Application
    Filed: May 13, 2021
    Publication date: June 8, 2023
    Inventors: Richard Charles Alfred SAINSON, Cecilia DEANTONIO, Chih-Hung HSU, Li-Chun LU, Lorcan Adrian SHERRY
  • Publication number: 20230170421
    Abstract: A transistor structure includes a substrate, an isolation wall, and a gate region. The substrate has a fin structure. The isolation wall clamps sidewalls of the fin structure. The gate region is above the fin structure and the isolation wall; wherein the isolation wall is configured to prevent the fin structure from collapsing.
    Type: Application
    Filed: November 24, 2022
    Publication date: June 1, 2023
    Applicant: Invention And Collaboration Laboratory Pte. Ltd.
    Inventors: Chao-Chun Lu, Li-Ping Huang
  • Publication number: 20230143986
    Abstract: A transistor structure includes a substrate, an isolation wall, and a gate region. The substrate has a fin structure. The isolation wall clamps sidewalls of the fin structure. The gate region is above the fin structure and the isolation wall. The isolation wall is configured to prevent the fin structure from collapsing.
    Type: Application
    Filed: November 8, 2022
    Publication date: May 11, 2023
    Applicant: Invention And Collaboration Laboratory Pte. Ltd.
    Inventor: Chao-Chun Lu
  • Patent number: 11643599
    Abstract: This invention pertains to slurries, methods and systems that can be used in chemical mechanical planarization (CMP) of tungsten containing semiconductor device. Using the CMP slurries with additives to counter lowering of pH by tungsten polishing byproducts and maintain pH 4 or higher, the erosion of dense metal (such as tungsten) structures can be greatly diminished.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: May 9, 2023
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Chun Lu, Xiaobo Shi, Dnyanesh Chandrakant Tamboli, Reinaldo Mario Machado, Mark Leonard O'Neill, Matthias Stender
  • Publication number: 20230131138
    Abstract: A multi-phase inductor structure is provided. The multi-phase inductor structure includes a first magnetic core, two second magnetic cores, and two first electrical conductors. The two second magnetic cores are respectively arranged on opposite sides of the first magnetic core, and each have a first engagement surface. A first annular convex wall and a first upright convex wall are formed on the first engagement surface, and a first recess is formed therebetween. The two first electrical conductors are respectively arranged in two of the first recesses of the first engagement surface, and each have has a first body and two first pins that are respectively connected to two ends of the first body. The two first pins extend in opposite directions. A magnetic permeability of the first magnetic core is different from a magnetic permeability of each of the two second magnetic cores.
    Type: Application
    Filed: March 14, 2022
    Publication date: April 27, 2023
    Inventors: HUNG-CHIH LIANG, PIN-YU CHEN, HSIU-FA YEH, HANG-CHUN LU, YA-WAN YANG, YU-TING HSU, WEI-ZHI HUANG
  • Publication number: 20230118711
    Abstract: The present disclosure provides a package device. The package device includes a first integrated circuit chip, a second integrated circuit chip, a first input/output pin, and a first electrostatic discharge protection element. The first integrated circuit chip includes a first internal circuit and a first input/output pad disposed on the first integrated circuit chip and coupled to the first internal circuit. The second integrated circuit chip is stacked on the first integrated circuit chip. The second integrated circuit chip includes a second internal circuit and a second input/output pad disposed on the second integrated circuit chip and coupled to the second internal circuit. The first input/output pin is coupled to the first integrated circuit chip and the second integrated circuit chip. The first electrostatic discharge protection element is coupled between the first input/output pad and the first internal circuit.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 20, 2023
    Inventor: Chun-Lu LEE
  • Publication number: 20230124176
    Abstract: A patent search system, comprising: a database storing a plurality of first patent document data items; and a server accessing the database, the server receiving a first search criterion instruction and then retrieving a plurality of second patent document data items from the plurality of first patent document data items based on the first search criterion instruction, wherein the server receives a first selection instruction associated with a first selected patent document data item in the plurality of second patent document data items, obtains a first keyword data item from the first selected patent document data item based on the first selection instruction, and generates a second search criterion instruction at least based on the first search criterion instruction and the first keyword data item, the second search criterion instruction comprising the first keyword data item, wherein the server retrieves a plurality of third patent document data items from the plurality of first patent document data items
    Type: Application
    Filed: April 14, 2022
    Publication date: April 20, 2023
    Applicant: KKLAB TECHNOLOGIES PTE. LTD.
    Inventors: Shih Chun Lu, Shih Hung Lin, Sheng Fu Lin
  • Patent number: 11629018
    Abstract: A feeding roller structure includes a fastening frame, a transmission component, a transmission roller and a floating coupler. The transmission component is assembled in the fastening frame. The transmission component includes a drive shaft mounted on two sides of the fastening frame. The transmission roller is concentrically arranged around the drive shaft. The floating coupler is mounted to the fastening frame. The floating coupler is coupled between the drive shaft and the transmission roller. Two opposite ends of the floating coupler are adjacent to and spaced from the two sides of the fastening frame to form two gaps. Each gap is formed between one end of the floating coupler and one side of the fastening frame. The two gaps limit an angular displacement of the floating coupler.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: April 18, 2023
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventors: Kuan Ting Chen, Jing Hua Fang, Pei Chun Lu