Abstract: A transistor structure includes a substrate, an isolation wall, and a gate region. The substrate has a fin structure. The isolation wall clamps sidewalls of the fin structure. The gate region is above the fin structure and the isolation wall; wherein the isolation wall is configured to prevent the fin structure from collapsing.

Abstract: A transistor structure includes a substrate, an isolation wall, and a gate region. The substrate has a fin structure. The isolation wall clamps sidewalls of the fin structure. The gate region is above the fin structure and the isolation wall. The isolation wall is configured to prevent the fin structure from collapsing.

Abstract: This invention pertains to slurries, methods and systems that can be used in chemical mechanical planarization (CMP) of tungsten containing semiconductor device. Using the CMP slurries with additives to counter lowering of pH by tungsten polishing byproducts and maintain pH 4 or higher, the erosion of dense metal (such as tungsten) structures can be greatly diminished.

Abstract: A multi-phase inductor structure is provided. The multi-phase inductor structure includes a first magnetic core, two second magnetic cores, and two first electrical conductors. The two second magnetic cores are respectively arranged on opposite sides of the first magnetic core, and each have a first engagement surface. A first annular convex wall and a first upright convex wall are formed on the first engagement surface, and a first recess is formed therebetween. The two first electrical conductors are respectively arranged in two of the first recesses of the first engagement surface, and each have has a first body and two first pins that are respectively connected to two ends of the first body. The two first pins extend in opposite directions. A magnetic permeability of the first magnetic core is different from a magnetic permeability of each of the two second magnetic cores.

Abstract: The present disclosure provides a package device. The package device includes a first integrated circuit chip, a second integrated circuit chip, a first input/output pin, and a first electrostatic discharge protection element. The first integrated circuit chip includes a first internal circuit and a first input/output pad disposed on the first integrated circuit chip and coupled to the first internal circuit. The second integrated circuit chip is stacked on the first integrated circuit chip. The second integrated circuit chip includes a second internal circuit and a second input/output pad disposed on the second integrated circuit chip and coupled to the second internal circuit. The first input/output pin is coupled to the first integrated circuit chip and the second integrated circuit chip. The first electrostatic discharge protection element is coupled between the first input/output pad and the first internal circuit.

Abstract: A patent search system, comprising: a database storing a plurality of first patent document data items; and a server accessing the database, the server receiving a first search criterion instruction and then retrieving a plurality of second patent document data items from the plurality of first patent document data items based on the first search criterion instruction, wherein the server receives a first selection instruction associated with a first selected patent document data item in the plurality of second patent document data items, obtains a first keyword data item from the first selected patent document data item based on the first selection instruction, and generates a second search criterion instruction at least based on the first search criterion instruction and the first keyword data item, the second search criterion instruction comprising the first keyword data item, wherein the server retrieves a plurality of third patent document data items from the plurality of first patent document data items

Abstract: A feeding roller structure includes a fastening frame, a transmission component, a transmission roller and a floating coupler. The transmission component is assembled in the fastening frame. The transmission component includes a drive shaft mounted on two sides of the fastening frame. The transmission roller is concentrically arranged around the drive shaft. The floating coupler is mounted to the fastening frame. The floating coupler is coupled between the drive shaft and the transmission roller. Two opposite ends of the floating coupler are adjacent to and spaced from the two sides of the fastening frame to form two gaps. Each gap is formed between one end of the floating coupler and one side of the fastening frame. The two gaps limit an angular displacement of the floating coupler.

Abstract: A depth processing system includes a plurality of depth capturing devices and a processor. Each depth capturing device of the plurality of depth capturing devices generates depth information corresponding to a field-of-view thereof according to the field-of-view. The processor fuses a plurality of depth information generated by the plurality of depth capturing devices to generate a three-dimensional point cloud/panorama depths corresponding to a specific region, and detects a moving object within the specific region according to the three-dimensional point cloud/the panorama depths.

Abstract: Compositions and methods are provided for potent mRNA vaccines for prevention and treatment of 2019 novel Coronavirus (2019-nCoV) infections. The compositions include a pharmaceutical composition containing one or more mRNA molecules encoding spike protein epitopes, including mutated epitopes, or mRNA cocktails that encode critical viral genes together with pharmaceutically acceptable polymeric nanoparticle carriers and liposomal nanoparticle carriers. Methods for stimulating system immune responses and treatment are provided, including subcutaneous, intraperitoneal and intramuscular injections.

Abstract: A SRAM cell structure includes a plurality of transistors, a set of contacts, a word-line, a bit-line, a VDD contacting line and a VSS contacting line. The plurality of transistors include n transistors, wherein n is a positive integral less than 6. The set of contacts are coupled to the plurality of transistors. The word-line is electrically coupled to the plurality of transistors. The bit-line and a bit line bar are electrically coupled to the plurality of transistors. The VDD contacting line is electrically coupled to the plurality of transistors. The VSS contacting line is electrically coupled to the plurality of transistors. Wherein as a minimum feature size of the SRAM cell structure gradually decreases from 28 nm, an area size of the SRAM cell in terms of square of the minimum feature size (?) is the same or substantially the same.

Abstract: A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.

Abstract: A device such as a stylus may have a color sensor. The color sensor may have a color sensing light detector having a plurality of photodetectors each of which measures light for a different respective color channel. The color sensor may also have a light emitter. The light emitter may have an adjustable light spectrum. The light spectrum may be adjusted during color sensing measurements using information such as ambient light color measurements made with a color ambient light sensor that has a plurality of photodetectors each of which measures light for a different respective color channel. An inertial measurement unit may be used to measure the angular orientation between the stylus and an external object during color measurements. Arrangements in which the light emitter is modulated during color sensing may also be used. Measurements from the stylus may be transmitted wirelessly to external equipment.

Abstract: A standard cell includes a plurality of transistors, a set of contacts coupled to the plurality of transistors, at least one input line electrically coupled to the plurality of transistors, an output line electrically coupled to the plurality of transistors, a VDD contacting line electrically coupled to the plurality of transistors and a VSS contacting line electrically coupled to the plurality of transistors. Wherein as a minimum feature size (?) of the standard cell gradually decreases from 22 nm, an area size of the standard cell in terms of ?2 is the same or substantially the same.

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

Abstract: The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.

Abstract: The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.

Abstract: A transistor structure includes a substrate, a gate conductive region, a gate dielectric layer, and a sheet channel layer. The substrate has a body region. The gate conductive region is above the body region. The gate dielectric layer is between the gate conductive region and the body region. The sheet channel layer is disposed between the body region and the gate dielectric layer, wherein the sheet channel layer is independent from the substrate. A doping concentration of the body region is higher than a doping concentration of the sheet channel layer.

Abstract: A transistor structure includes a substrate, a gate conductive region, a gate dielectric layer and a first conductive region. At least a portion of the gate conductive region is disposed below a surface of the substrate. The gate dielectric layer surrounds a bottom wall and sidewalls of the gate conductive region. A bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

Abstract: A method for forming a transistor structure includes steps as follows: A substrate with an original surface is prepared. Next a gate conductive region is formed, wherein at least a portion of the gate conductive region is disposed below the original surface, and a bottom wall and sidewalls of the gate conductive region is surrounded by a gate dielectric layer. Then, a first conductive region is formed, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.