Patents by Inventor Chun-Chen Yeh

Chun-Chen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190181012
    Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.
    Type: Application
    Filed: February 1, 2019
    Publication date: June 13, 2019
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20190180185
    Abstract: A computer-implemented method for training a random matrix network is presented. The method includes initializing a random matrix, inputting a plurality of first vectors into the random matrix, and outputting a plurality of second vectors from the random matrix to be fed back into the random matrix for training. The random matrix can include a plurality of two-terminal devices or a plurality of three-terminal devices or a film-based device.
    Type: Application
    Filed: December 8, 2017
    Publication date: June 13, 2019
    Inventors: Xiao Sun, Youngseok Kim, Chun-Chen Yeh
  • Patent number: 10317646
    Abstract: An optical imaging module includes six lens elements, the six lens elements being, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. The first lens element has negative refractive power. The second lens element has an image-side surface being concave. The third lens element has an image-side surface being convex. The fourth lens element has positive refractive power. The fifth lens element with negative refractive power has an object-side surface being concave and an image-side surface being convex. The sixth lens element has an image-side surface being concave, wherein an object-side surface and the image-side surface of the sixth lens element are both aspheric, and the image-side surface of the sixth lens element includes at least one inflection point.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: June 11, 2019
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Cheng-Chen Lin, Chun-Yen Chen, Yu-Tai Tseng, Kuan-Ting Yeh, Hsin-Hsuan Huang
  • Patent number: 10319840
    Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10319731
    Abstract: The disclosure is directed to an integrated circuit structure and method of forming the same. The integrated circuit structure may include: a first device region including: a floating gate structure substantially surrounding a first fin that is over a substrate; a first bottom source/drain within the substrate, and beneath the first fin and the floating gate structure; a first top source/drain over the first fin and the floating gate structure; a first spacer substantially surrounding the first top source/drain and disposed over the floating gate structure; and a gate structure substantially surrounding and insulated from the floating gate structure, the gate structure being disposed over the substrate and having a height greater than a height of the floating gate.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: June 11, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita, Kangguo Cheng
  • Patent number: 10312377
    Abstract: Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners. There is a gate stack on the channel region of the one or more semiconductor fins.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 4, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Veeraraghavan S. Basker, Shogo Mochizuki, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20190165142
    Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.
    Type: Application
    Filed: February 1, 2019
    Publication date: May 30, 2019
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10304747
    Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: May 28, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC
    Inventors: Balasubramanian Pranatharthiharan, Ruilong Xie, Chun-Chen Yeh
  • Publication number: 20190157457
    Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 23, 2019
    Inventors: Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh
  • Patent number: 10297452
    Abstract: One illustrative method disclosed includes selectively forming sacrificial conductive source/drain cap structures on and in contact with first and second source/drain contact structures positioned on opposite sides of a gate of a transistor and removing and replacing the spaced-apart sacrificial conductive source/drain cap structures with first and second separate, laterally spaced-apart insulating source/drain cap structures that are positioned on the first and second source/drain contact structures. The method also includes forming a gate contact opening that extends through a space between the insulating source/drain cap structures and through the gate cap so as to expose a portion of the gate structure and forming a conductive gate contact structure (CB) that is conductively coupled to the gate structure.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Hui Zang, Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20190148362
    Abstract: Fabricating a semiconductor device includes receiving a substrate structure including a substrate. The substrate structure further includes a first bottom source/drain and a first fin formed on a vertical transistor portion of the substrate and a second bottom source/drain and a second fin formed on a varactor portion of the substrate. The substrate structure further includes a bottom spacer formed on the first bottom source/drain of the vertical transistor portion and the second bottom source/drain of the varactor portion. A mask is applied to the portion of the bottom spacer formed on the first bottom source/drain. The portion of the bottom spacer formed on the second bottom source/drain of the varactor portion is removed. The mask is removed from the portion of the bottom spacer formed on the first bottom source/drain. A gate oxide is deposited on the vertical transistor portion and the varactor portion.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 16, 2019
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ruilong Xie, TENKO YAMASHITA, CHUN-CHEN YEH
  • Publication number: 20190148377
    Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 16, 2019
    Applicant: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20190148360
    Abstract: Fabricating a semiconductor device includes receiving a substrate structure including a substrate. The substrate structure further includes a first bottom source/drain and a first fin formed on a vertical transistor portion of the substrate and a second bottom source/drain and a second fin formed on a varactor portion of the substrate. The substrate structure further includes a bottom spacer formed on the first bottom source/drain of the vertical transistor portion and the second bottom source/drain of the varactor portion. A mask is applied to the portion of the bottom spacer formed on the first bottom source/drain. The portion of the bottom spacer formed on the second bottom source/drain of the varactor portion is removed. The mask is removed from the portion of the bottom spacer formed on the first bottom source/drain. A gate oxide is deposited on the vertical transistor portion and the varactor portion.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 16, 2019
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ruilong Xie, TENKO YAMASHITA, CHUN-CHEN YEH
  • Patent number: 10290636
    Abstract: A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: May 14, 2019
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Qing Liu, Chun-chen Yeh, Ruilong Xie, Xiuyu Cai
  • Patent number: 10283423
    Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tenko Yamashita, Chun-Chen Yeh, Hui Zang
  • Patent number: 10276573
    Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: April 30, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie, Chun-chen Yeh
  • Patent number: 10276659
    Abstract: A vertical transistor device includes a vertically-oriented channel semiconductor (VOCS) structure positioned above a substrate and a first bottom spacer positioned above the substrate adjacent the VOCS structure. The first bottom spacer extends around less than an entirety of a perimeter of the VOCS structure. A gate structure is positioned around the VOCS structure. Only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure. The air gap extends around a majority of a perimeter of the VOCS structure and a second bottom spacer positioned above the substrate. An upper portion of the second bottom spacer contacts a material formed around the VOCS structure so as to seal the air gap. The second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chun-Chen Yeh, Kangguo Cheng, Tenko Yamashita
  • Publication number: 20190123178
    Abstract: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 25, 2019
    Inventors: Effendi Leobandung, Chun-chen Yeh
  • Patent number: 10269920
    Abstract: Provided is a method for forming a semiconductor structure. In embodiments, the method includes forming multiple channel nanosheets in multiple first stacks over a substrate. The channel nanosheets in the first stack define first stack cavities such that each pair of adjacent stacked channel nanosheets in the first stack is separated by one of the first stack cavities. The method further includes forming multiple channel nanosheets in a second stack over a substrate. The channel nanosheets in the second stack defining second stack cavities such that each pair of adjacent stacked channel nanosheets in the first second is separated by one of the second stack cavities. The method further includes filling the first stack cavities with a first gate dielectric material and filling the second stack cavities with a work function metal and a second gate dielectric material. The first gate dielectric material differs from the second gate dielectric material.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10269983
    Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A fin is formed that includes a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack. A cavity is formed between a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer. An epitaxially-grown source/drain region is connected with the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer. A gate structure is formed that includes a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer. The cavity is surrounded by the first nanosheet channel layer, the second nanosheet channel layer, the section of the gate structure, and the source/drain region to define an air gap spacer.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: April 23, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ruilong Xie, Hui Zang, Kangguo Cheng, Tenko Yamashita, Chun-chen Yeh