Abstract: A method for manufacturing a semiconductor device includes forming a plurality of semiconductor layers on a semiconductor substrate, and forming a plurality of gate structures spaced apart from each other on the semiconductor layers. The semiconductor layers are patterned into a plurality of patterned stacks spaced apart from each other, wherein the plurality of patterned stacks are under the plurality of gate structures. The method also includes forming a plurality of sacrificial spacers on lateral sides of the plurality of gate structures, and growing a plurality of source/drain regions. The source/drain regions are adjacent the patterned stacks and include a plurality of pillar portions formed on lateral sides of the sacrificial spacers. The sacrificial spacers and the plurality of pillar portions are removed.

Abstract: A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.

Abstract: Embodiments of the invention are directed to a method that includes forming a first sacrificial nanosheet over a substrate and forming a first nanosheet stack over the first sacrificial nanosheet. A cavity is formed under the first nanosheet stack by removing at least a first portion of the first sacrificial nanosheet and leaving a second portion of the first sacrificial nanosheet. An isolation material is deposited within the cavity to form a first isolation region. A portion of the first nanosheet stack that is above the second portion of the first sacrificial nanosheet is removed to separate the first nanosheet stack into a second nanosheet stack and a third nanosheet stack. The second portion of the first sacrificial nanosheet is replaced with the isolation material to form a second isolation region. A bottom isolation region includes the first isolation region and the second isolation region.

Abstract: Embodiments of the invention are directed to a method that includes forming a first sacrificial nanosheet over a substrate and forming a first nanosheet stack over the first sacrificial nanosheet. A cavity is formed under the first nanosheet stack by removing at least a first portion of the first sacrificial nanosheet and leaving a second portion of the first sacrificial nanosheet. An isolation material is deposited within the cavity to form a first isolation region. A portion of the first nanosheet stack that is above the second portion of the first sacrificial nanosheet is removed to separate the first nanosheet stack into a second nanosheet stack and a third nanosheet stack. The second portion of the first sacrificial nanosheet is replaced with the isolation material to form a second isolation region. A bottom isolation region includes the first isolation region and the second isolation region.

Abstract: An integrated circuit having logic and static random-access memory (SRAM) devices includes at least three active regions with gate terminals. Dielectric pillars are disposed between the active regions of the integrated circuit. A pillar is disposed symmetrically between two active regions of the logic device. A pillar is disposed asymmetrically between a p-channel field effect transistor (pFET), and an n-channel field effect transistor (nFET) of the SRAM device.

Abstract: A vertical field effect transistor (VFET) having a bottom airgap spacer located beneath a gate structure and a top airgap spacer located above the gate structure is provided. The top airgap spacer reduces overlap capacitance between the gate structure and a top source/drain structure of the VFET, while the bottom airgap spacer reduces the overlap capacitance and a coupling capacitance that is present between the gate structure and a bottom source/drain structure of the VFET.

Abstract: A method is presented for limiting lateral protrusion of neighboring epitaxial growths. The method includes masking an n-type field effect transistor (NFET) region of a semiconductor substrate with a first mask, forming first epitaxial source/drain regions in a p-type field effect transistor (PFET) region, where the first mask limits lateral growth of the first epitaxial source/drain regions in the PFET region toward the NFET region, masking the PFET region of the semiconductor substrate with a second mask, and forming second epitaxial source/drain regions in the NFET region, where the second mask limits lateral growth of the second epitaxial source/drain regions in the NFET region toward the PFET region.

Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.

Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.

Abstract: Semiconductor fins of a monolithic semiconductor structure are electrically isolated using a dielectric material at the bottoms of the fins. Relatively tall semiconductor fins can be fabricated at a relatively narrow fin pitch while avoiding mechanical instability. The semiconductor fins are grown on sidewalls of semiconductor mandrels and over a dielectric layer. The semiconductor fins are supported during mandrel removal to provide mechanical stability. The semiconductor fins can be employed as channel regions of FinFET devices.

Abstract: Self-limiting cavities are formed within a crystalline semiconductor substrate and beneath a stack of semiconductor layers used to form a nanosheet transistor device. Inner ends of the cavities merge beneath the stack while the outer ends thereof adjoin isolation regions within the substrate. The cavities are filled with electrically insulating material to provide bottom device isolation. Source/drain regions are grown in vertical trenches extending through the stack of semiconductor layers following formation of dielectric inner spacers. The bottom ends of the trenches adjoin the electrically insulating material within the cavities.

Abstract: A vertical field effect transistor (VFET) having a bottom airgap spacer located beneath a gate structure and a top airgap spacer located above the gate structure is provided. The top airgap spacer reduces overlap capacitance between the gate structure and a top source/drain structure of the VFET, while the bottom airgap spacer reduces the overlap capacitance and a coupling capacitance that is present between the gate structure and a bottom source/drain structure of the VFET.

Abstract: A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.

Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.

Abstract: A method is presented for limiting lateral protrusion of neighboring epitaxial growths. The method includes masking an n-type field effect transistor (NFET) region of a semiconductor substrate with a first mask, forming first epitaxial source/drain regions in a p-type field effect transistor (PFET) region, where the first mask limits lateral growth of the first epitaxial source/drain regions in the PFET region toward the NFET region, masking the PFET region of the semiconductor substrate with a second mask, and forming second epitaxial source/drain regions in the NFET region, where the second mask limits lateral growth of the second epitaxial source/drain regions in the NFET region toward the PFET region.

Abstract: Structures including a vertical-transport field-effect transistor and a planar field-effect transistor, and methods of forming such structures. First and second sacrificial fins are respectively formed over first and second areas of the first device region. One or more semiconductor fins of the vertical-transport field-effect transistor are formed over the second device region. A first gate electrode of the planar field-effect transistor, which is arranged on the first device region between the first sacrificial fin and the second sacrificial fin, and a second gate electrode of the vertical-transport field-effect transistor, which is wrapped about the one or more semiconductor fins, are currently formed.

Abstract: A method is presented for constructing mechanically stable fins. The method includes forming a fin stack including a plurality of sacrificial layers, recessing the fin stack to form channel fins, depositing a first type epitaxy between the channel fins, depositing a dielectric region over the first type epitaxy, depositing a second type epitaxy over the dielectric region, and removing the plurality of sacrificial layers resulting in formation of a plurality of gaps. The method further includes filling a first set of the plurality of gaps with a p-type work function metal (WFM) to form a p-type field effect transistor (pFET) structure and filling a second set of the plurality of gaps with an n-type WFM to form an n-type field effect transistor (nFET) structure, where the nFET structure is stacked over the pFET structure.

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Abstract: Semiconductor fins of a monolithic semiconductor structure are electrically isolated using a dielectric material at the bottoms of the fins. Relatively tall semiconductor fins can be fabricated at a relatively narrow fin pitch while avoiding mechanical instability. The semiconductor fins are grown on sidewalls of semiconductor mandrels and over a dielectric layer. The semiconductor fins are supported during mandrel removal to provide mechanical stability. The semiconductor fins can be employed as channel regions of FinFET devices.